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s3c8639/c863a/p863a/c8647/f8647 product overview 1- 1 1 product overview sam8 product family samsung's sam8 family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu with a wide range of integrated peripherals, in variou s mask-programmable rom sizes. analog its major cpu features are : ? efficient register-oriented architecture ? selectable cpu clock sources ? idle and stop power-down mode release by interrupt ? built-in basic timer with watchdog function the sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum of four cpu clocks) can be assigned to specific interrupt levels. s3c8639/c863a/p863a microcontrollers s3c8639/c863a/p863a single-chip 8-bit microcontroller s are based on the powerful sam8 cpu architecture. the internal register file is logically expanded to incre ase the on-chip register space. s3c8639/c863a/p863a contain 32/48 k bytes of on- chip program rom. in line with samsung's modular design approach, the following peripherals are integrated with the sam8 core: ? f our programmable i/o ports (total 27 pins) ? one 8-bit basic timer for oscillation stabilization and watchdog functions ? one 8-bit general-purpose timer/counter with selectable clock sources ? one interval timer ? one 12 -bit counter with selectable clock sources, including hsync or csync input ? pwm block with seven 8-bit pwm circuits ? sync processor block (for vsync and hsync i/o, csync input, and clamp signal output) ? ddc multi-master and slave-only iic-bus ? 4-channel a/d converter (8-bit resolution) s3c8639/c863a/p863a are a versatile microcontroller s which are ideal for use in multi-sync monitors or in general-purpose applications that require sophisticated timer/counter, pwm, sync signal processing, a/d converter, and multi-master iic-bus support with ddc. they are available in a 42-pi n sdip or a 44 -pin qfp package. otp s3c8639/c863a microcontrollers are also available in otp (one time programmable) version named, s3p863a. s3p863a microcontroller has an on-chip 48-kbyte one-time-programmable eprom instead of masked rom. s3p863a is comparable to s3c8639/c863a, both in function and pin configuration except its rom size.
product overview s3c8639/c863a/p863a /c8647/f8647 1- 2 s3c8647/f8647 microcontrollers s3c8647/f8647 single-chip 8-bit microcontroller s are based on the powerful sam8 cpu architecture. the internal register file is logically expanded to incre ase the on-chip register space. s3c8647/f8647 contain 24 k bytes of on-chip program rom. in line with samsung's modular design approach, the following peripherals are integrated with the sam8 core: ? three programmable i/o ports (total 19 pins) ? one 8-bit basic timer for oscillation stabilization and watchdog functions ? one 8-bit general-purpose timer/counter with selectable clock sources ? one interval timer ? one 12 -bit counter with selectable clock sources, including hsync or csync input ? pwm block with six 8-bit pwm circuits ? sync processor block (for vsync and hsync i/o, csync input, and clamp signal output) ? ddc multi-master iic-bus ? 4-channel a/d converter (4-bit resolution) s3c8647/f8647 are a versatile microcontroller s which are ideal for use in multi-sync monitors or in general-purpose applications that require sophisticated timer/counter, pwm, sync signal processing, a/d converter, and multi-master iic-bus support with ddc. they are available in a 3 2-pi n sdip/sop package. flash s3c8647 microcontroller is also available in flash version named, S3F8647. S3F8647 microcontroller has an on-chip 24-kbyte flash cells instead of masked rom. S3F8647 is comparable to s3c8647, both in function and pin configuration.
s3c8639/c863a/p863a/c8647/f8647 product overview 1- 3 features cpu ? sam 88rc cpu core memory ? s3c8639: 32-kbyte program memory (rom) s3c863a: 48-kbyte program memory (rom) s3c8647: 24-kbyte program memory (rom) ? s3c8639: 784-byte general-purpose register area s3c863a: 1040- byte general-purpose register area s3c8647: 400-byte general-purpose register area instruction set ? 78 instructions ? idle and stop instructions added for power-down modes instruction execution time ? minimum 333 ns (with 12 mhz cpu clock) interrupts ? ten (nine)* interrupt sources/vectors (s3c8647)* ? eight (seven)* interrupt level (s3c8647)* ? fast interrupt feature general i/o ? s3c863x: four i/o ports (total 27pins) s3c8647: three i/o ports (total 19pins) 8-bit basic timer ? programmable timer for oscillation stabilization interval control or watchdog timer function ? three selective internal clock frequencies timer/counters ? one 8-bit timer/counter with several clock sources (capture mode) ? one 12-bit counter with h-/c-sync and several clock sources ? one interval timer low voltage detector (lvd & por) pulse width modulator (pwm) ? 8-bit pwm: 7(6)*-ch (s3c8647)* (6-bit basic frame with 2-bit extension) sync-processor block ? vsync-i, hsync-i, csync-i input and vsync-o, hsync-o, clamp-o output pins ? programmable pseudo sync signal generation ? auto sog detection ? auto h-/v-sync polarity detection ? composite sync detection ddc multi-master iic-bus 1-ch ? serial peripheral interface ? support for display data channel (ddc1/ddc2b/ddc2bi/ddc2b+) slave only iic-bus 1-ch (only s3c863x) ? serial peripheral interface a/d converter ? 4-channel; 8(4)*-bit resolution (s3c8647)* oscillator frequency ? 8 mhz to 12 mhz crystal operation ? internal max. 12 mhz cpu clock operating temperature range ? ? 40 c to + 85 c operating voltage range ? 3.0(4.0)* v to 5.5 v (s3c8647)* package types ? s3c863x: 42-pin sdip, 44-pin qfp s3c8647: 32-pin sdip, 32-pin sop
product overview s3c8639/c863a/p863a /c8647/f8647 1- 4 block diagram port 0 p0.0-p0.7/int0-int2 i/o port and interrupt control 32/48- kbyte rom 784/1040- byte register file sam8 cpu port 2 port 1 p1.0-p1.2 p2.0-p2.7 v dd1 , v dd2 v ss1 , v ss2 test reset int0-int2 adc port 3 p3.0-p3.7 slave only iic-bus ad0-ad3 scl1 sda1 main osc 8-bit pwm (7-ch) sync- processor x out x in pwm0 pwm6 8-bit counter (timer m0) tm0cap vsync-i hsync-i csync-i vsync-o hsync-o clamp-o 12-bit counter (timer m1) interval timer (timer m2) multi-master iic-bus and ddc1/2b/2bi/2b+ scl0 sda0 * s3c8639 - 32 kbyte rom - 784 byte ram * s3c863a - 48 kbyte rom - 1040 byte ram figure 1- 1. block diagram (s3c863x)
s3c8639/c863a/p863a/c8647/f8647 product overview 1- 5 port 0 p0.0-p0.2, p0.4/ int0-int2 i/o port and interrupt control 32/48-kbyte rom 400-byte register file sam8 cpu port 2 p2.0-p2.5, p2.7 v dd v ss test reset int0-int2 8-bit counter (timer m0) interval timer (timer m2) mt0cap sync- processor vsync-i hsync-i csync-i vsync-o hsync-o clamp-o 8-bit pwm (6-ch) pwm0 pwm5 main osc x out x in port 3 p3.0-p3.7 multi- master iic-bus (ddc1/ 2b/2bi/ 2b+) scl0 vclk sda0 12-bit counter (timer m1) adc ad0-ad3 figure 1- 2. block diagram (s3c8647)
product overview s3c8639/c863a/p863a /c8647/f8647 1- 6 pin assignments p0.0/int0 p0.1/int1 p0.2/int2 p0.3 p0.4/tm0cap p0.5 p0.6 p0.7 p1.0/sda1 p1.1/scl1 v dd1 v ss1 x out x in test (gnd) sda0 scl0 reset p1.2 p2.0/pwm0 p2.1/pwm1 s3c8639/c863a (42-sdip) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p3.7 p3.6 p3.5 p3.4 p3.3/ad3 p3.2/ad2 p3.1/ad1 p3.0/ad0 v dd2 v ss2 p2.7/csync-i (sog) hsync-i vsync-i vsync-o hsync-o clamp-o p2.6/pwm6 p2.5/pwm5 p2.4/pwm4 p2.3/pwm3 p2.2/pwm2 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 note: the test pin must connect to v ss (gnd) in the normal operation mode. figure 1- 3 . s3c8639/c863a pin assignment (42-sdip)
s3c8639/c863a/p863a/c8647/f8647 product overview 1- 7 scl0 reset p1.2 p2.0/pwm0 p2.1/pwm1 p2.2/pwm2 n.c. p2.3/pwm3 p2.4/pwm4 p2.5/pwm5 p2.6/pwm6 p3.2/ad2 p3.1/ad1 p3.0/ad0 v dd2 v ss2 p2.7/csync-i (sog) hsync-i vsync-i vsync-o hsync-o clamp-o p0.4/tm0cap p0.3 p0.2/int2 p0.1/int1 n.c. p0.0/int0 p3.7 p3.6 p3.5 p3.4 p3.3/ad3 p0.5 p0.6 p0.7 p1.0/sda1 p1.1/scl1 v dd1 v ss1 x out x in test (gnd) sda0 s3c8639/c863a (44-qfp) 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 note: the test pin must connect to v ss (gnd) in the normal operation mode. figure 1- 4 . s3c8639/c863a pin assignment (44-qfp)
product overview s3c8639/c863a/p863a /c8647/f8647 1- 8 v ss x out x in test p0.0/int0 p0.1/int1 reset p0.2/int2 p0.4/tm0cap sda scl p2.0/pwm0 p2.1/pwm1 p2.2/pwm2 p2.3/pwm3 p2.4/pwm4 s3c8647 (32-sdip) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd p3.7 p3.6 p3.5 p3.4 p3.3/ad3 p3.2/ad2 p3.1/ad1 p3.0/ad0 p2.7/csync-i(sog) hsync-i vsync-i vsync-o hsync-o clamp-o p2.5/pwm5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 figure 1- 5 . s3c8647 pin assignment (32-sdip) s3c8647 (32-sop) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v ss x out x in test p0.0/int0 p0.1/int1 reset p0.2/int2 p0.4/tm0cap sda scl p2.0/pwm0 p2.1/pwm1 p2.2/pwm2 p2.3/pwm3 p2.4/pwm4 v dd p3.7 p3.6 p3.5 p3.4 p3.3/ad3 p3.2/ad2 p3.1/ad1 p3.0/ad0 p2.7/csync-i(sog) hsync-i vsync-i vsync-o hsync-o clamp-o p2.5/pwm5 figure 1-6. s3c8647 pin assignment (32-sop)
s3c8639/c863a/p863a/c8647/f8647 product overview 1- 9 pin descriptions table 1-1. s3c8639/c863a pin descriptions pin names pin type pin description circuit type sdip pin numbers shared functions p0.0 p0.1 p0.2 p0.3 (note) p0.4 p0.5 (note) p0.6 (note) p0.7 (note) i/o general-purpose, 8-bit i/o port. shared functions include three external interrupt inputs and i/o for timer m0. selective configuration of port 0 pins to input or output mode is supported. d-1 d-1 d-1 d-1 d-1 d-1 d-1 d-1 1 2 3 4 5 6 7 8 int0 int1 int2 tm0cap p1.0 (note) p1.1 (note) p1.2 (note) i/o general-purpose, 8-bit i/o port. selective configuration is available for port 1 pins to input, push-pull output, n-channel open-drain mode, or iic-bus clock and data i/o. e-1 e-1 e-1 9 10 19 sda1 scl1 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 (note) p2.7 i/o general-purpose, 8-bit i/o port selective configuration of port 2 pins to input or output mode is supported. the port 2 pin circuits are designed to push-pull pwm output and csync (sog) signal input. d-1 d-1 d-1 d-1 e-1 e-1 e-1 d-1 20 21 22 23 24 25 26 32 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 csync-i p3.0?p3.3 p3.4?p3.7 i/o general-purpose, 8-bit i/o port selective configuration port 3 pins to input or output mode is supported. multiplexed for alternative use as a/d converter inputs ad0?ad3. e-1 e 35?38 39?42 ad0? ad3 hsync-i vsync-i clamp-o hsync-o vsync-o sda0 scl0 i i o o o i/o i/o the pins are sync processor signal i/o and iic-bus clock and data i/o. a-3 a-3 a a a g-3 g-3 31 30 27 28 29 16 17 ? v dd1 , v ss1 (note) , v dd2 , v ss2 (note) ? power pins ? ? 11, 12 34, 33 ? x in , x out ? system clock i/o pins ? 14, 13 ? reset i system reset pin b 18 ? test i factory test pin input 0 v: normal operation , 5 v: factory test mode ? 15 ? note: not used in s3c8647.
product overview s3c8639/c863a/p863a /c8647/f8647 1- 10 pin circuits diagram data v ss output v dd figure 1- 7 . pin circuit type a reset v dd 280 k w noise filter figure 1- 9 . pin circuit type b ( reset reset ) input v ss output v ss 300 k w typical v dd figure 1- 8 . pin circuit type a-3 data or other function v ss output output disable digital input, ttl input note: the noise filter must be built in the external interrupts. v dd figure 1-10. pin circuit type d-1
s3c8639/c863a/p863a/c8647/f8647 product overview 1- 11 data v ss output typical 47 k w pull-up enable v dd v dd output disable open drain input figure 1-11. pin circuit type e v ss output data input figure 1-13. pin circuit type g-3 data v ss output v dd output disable open drain digital input or adc input figure 1-12. pin circuit type e-1
product overview s3c8639/c863a/p863a /c8647/f8647 1- 12 notes
s3c8639/c863a/p863a/c8647/f8647 address spaces 2- 1 2 address spaces overview s3c8639/c863a/c8647 microcontroller s ha ve two types of address space: ? internal program memory (rom) ? internal register file the 16-bit address and data bus support program memory operations. the separate 8 -bit register bus carries addresses and data between the cpu and the internal register file. s3c8639/c863a/c8647 employ an internal 32/48/24 -kbyte mask-programmable rom. e xternal memory interface is not implemented. there are 852/1108/462 8-bit registers in the internal register file. in this space, there are 784/1040/400 registers for general use, 19 for cpu and system control, and 49(43) for peripheral control and data. a n area of 16 -byte common working register (scratch) is part of the general-purpose register space. most of these registers serve as either a source or destination address, or as accumulators for data memory operations.
address spaces s3c8639/c863a/p863a /c8647/f8647 2- 2 program memory (rom) program memory (rom) stores program code or table data. s3c8639/c863a employ 32/48-k bytes of mask-programmable program memory. the memory address range is 0h? 7 fffh /bfffh (see figure 2-1). s3c8647 employs 24-kbytes of mask-programmable program memory. the memory address large is 0h-5fffh. the first 256 bytes of the rom (0h ? ffh) are reserved for interrupt vector addresses. un occupied locations in the address range can be used as normal program memory. when you use the vector address area to store program code, be careful not to overwrit e vector addresses stored in these locations. the rom address at which program execution starts after a reset is 0100h. 49,151 (decimal) interrupt vector area 48-kbyte internal program memory bfffh (hex) 32,767 255 0 24-kbyte internal program memory 7fffh 0h s3c8639 s3c863a 0ffh 24,575 32-kbyte s3c8647 figure 2-1. program memory address space
s3c8639/c863a/p863a/c8647/f8647 address spaces 2- 3 register architecture the upper 64-byte area of the s3c8639/c863a/c8647 file s is logically expanded to two 64-byte areas, called set 1 and set 2 . the upper 32-byte area of set 1 is divided into two register banks, bank 0 and bank 1 . the total physical register space is thereby expanded internal register to 864/1120 bytes. within this physical space, there ar e 864/1120/462-byte registers, of which 852/1108/450 are addressable. given the microcontroller?s 8-bit register bus architecture, up to 256 bytes of physical register space can be addressed as a single page . the s3c8639 register files have three pages, page 0, page 1 and page 2. and the s3c863a register files have four pages, page 0, page 1, page 2 and page 3. the s3c8647 register files have two pages, page 0, and page 1. all page contain 256 bytes respectively. the extension of physical register space into separately addressable areas (sets, banks, and pages) is enabled by addressing mode restrictions, the select bank instructions sb0 and sb1, and the register page pointer, pp. specific register types and area s (in bytes) they occupy in the s3c8639/c863a/c8647 internal register file s are summarized in table 2-1. table 2-1. register type summary register type number of bytes (s3c8639/c863a) number of bytes (s3c8647) general-purpose registers (including the 16-byte common working register area) 784/1040 400 cpu and system control registers 19 19 clock, peripheral, i/o control , and data registers 49 43 total addressable bytes 852/1108 462
address spaces s3c8639/c863a/p863a /c8647/f8647 2- 4 page 3 ~ page 2 ~ page 1 ~ d0h cfh e0h dfh c0h system and peripheral control registers system registers working registers ffh bank 0 bank 1 set 1 32 bytes 64 bytes e0h 192 bytes ffh c0h bfh note: to address registers in bank 0, bank 1, and the system register area, you must use the register addressing mode. to address working registers, you must use working register addressing mode. 00h 256 bytes page 0 general purpose data registers (indirect register, indexed addressing modes or stack operations) prime data registers (all addressing modes) ~ set 2 (s3c863a only) figure 2-2. internal register file organization (s3c863x)
s3c8639/c863a/p863a/c8647/f8647 address spaces 2- 5 ffh fch e0h d0h c0h set 1 bank 0 bank 1 ffh f2h c0h 00h ffh bfh page 0 set 2 dfh 00h 7fh page 1 general-purpose registers file peripheral registers and i/o ports working registers only cpu control and system registers not mapped figure 2- 3 . register file layout (s3c8647)
address spaces s3c8639/c863a/p863a /c8647/f8647 2- 6 register page pointer (pp) the sam8 architecture supports the logical expansion of the physical 256-byte internal register f ile (which use an 8-bit data bus) to as many as 1 6 separately addressable register pages. page addressing is controlled by the register page pointer (pp, dfh). two logical pages are implemented in s3c8639/c863a/c8647. these pages are used as general purpose register space. source: page 0 source: page 1 source: page 2 (not used for the s3c8647) source: page 3 (not used for the s3c8639) not used for the s3c8639/c863a/c8647 not used for the s3c8639/c863a/c8647 register page pointer (pp) dfh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb destination register page seleciton bits: 0 0 0 0 b 0 0 0 1 b 0 0 1 0 b 0 0 1 1 b 0 1 0 0 b 1 1 1 1 b destination: page 0 destination: page 1 destination: page 2 (not used for the s3c8647) destination: page 3 (not used for the s3c8639) not used for the s3c8639/c863a/c8647 not used for the s3c8639/c863a/c8647 source register page selection bits: 0 0 0 0 b 0 0 0 1 b 0 0 1 0 b 0 0 1 1 b 0 1 0 0 b 1 1 1 1 b figure 2- 4 . register page pointer (pp) register set 1 the term set 1 refers to the upper 64 bytes of the register file, locations c0h?ffh. the upper 32-byte area of this 64-byte space (e0h?ffh) is divided into two 32-byte register banks, bank 0 and bank 1 . you execute the set register bank instructions sb0 or sb1 to address one bank or the other. bank 0 is automatically selected by a reset operation. in s3c8639/c863a , register locations of only e0h? f4 h are addressable in the bank 1 area; the remaining locations ( f5 h ? ffh) are not mapped. the lower 32-byte area of set 1 is not banked and can be addressed at any time. it contains 16 mapped system registers (d0h?dfh) and a 16-byte ?scratch? area (c0h ? cfh) for working register addressing. registers in set 1 are directly accessible at all times using register addressing mode. the 16-byte working register area can only be accessed using working register addressing. (for more information about working register addressing, please refer to chapter 3, ?addressing modes . ?) register set 2 the same 64-byte physical space that is used for set 1 register locations c0h ? ffh is logically duplicated to add another 64 bytes of space. this expanded area of the register file is called set 2 . all set 2 locations (c0h? ffh) can be addressed in all page of the s3c8639/c863a register space. the logical division of set 1 and set 2 is maintai ned by means of addressing mode. in order to access set 1, you should use resister addressing mode. when you want to access register locations in set 2, you have to select register indirect addressing mode or indexed addressing mode access register locations in set 2.
s3c8639/c863a/p863a/c8647/f8647 address spaces 2- 7 prime register space the lower 192 bytes of the 256-byte physical internal register file (00h?bfh) is called the prime register space , or more simply, the prime area . you can access registers in this address range a t all page using any of the seven explicit addressing modes (see chapter 3, " addressing m odes " ). all registers in the prime area can be addressed immediately after a reset. prime area page 3 ~ set 2 prime area page 2 ~ set 2 ~ prime area page 1 ~ set 2 ffh fch e0h dfh cfh c0h set 1 rp0 = 1 1 0 0 0 0 0 0 rp1 = 1 1 0 0 1 0 0 0 register pointers rp0 and rp1 point to the common working register area, locations c0h-cfh, after a reset. ffh c0h bfh 00h ffh c0h bfh 00h page 0 set 2 prime area ~ ~ (s3c863a only) figure 2- 5 . set 1, set 2, and prime area register map (s3c863x)
address spaces s3c8639/c863a/p863a /c8647/f8647 2- 8 page 1 ffh fch e0h dfh cfh c0h set 1 rp0 = 1 1 0 0 0 0 0 0 rp1 = 1 1 0 0 1 0 0 0 register pointers rp0 and rp1 point to the common working register area, locations c0h-cfh, after a reset. ffh c0h bfh 00h page 0 set 2 prime area ~ ~ prime area 7fh 00h figure 2- 6 . set 1, set 2, and prime area register map (s3c8647)
s3c8639/c863a/p863a/c8647/f8647 address spaces 2- 9 working registers instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. when 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices." each slice comprises of eight 8-bit registers. with the two 8-bit register pointers, rp1 and rp0 employed , two working register slices can be selected at any time to form a 16-byte working register block. t he register pointers help , you move this 16-byte register block to anywhere in the addressable register file, except for the set 2 area. the terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces: ? o ne working register slice is 8 bytes (eight 8-bit working registers; r0?r7 or r8?r15) ? one working register block is 16 bytes (sixteen 8-bit working registers; r0?r15) all the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. this makes it possible for each register pointer to point to one of the 24 slices in the register file. the base addresses for the two 8-byte register slices selected are contained in register pointers rp0 and rp1. after a reset, rp0 and rp1 always point to the 16-byte common area in set 1 (c0h?cfh). each register pointer points to one 8-byte slice of the register space, selecting a total of 16-byte working register block. 1 1 1 1 1 x x x rp1 (registers r8-r15) rp0 (registers r0-r7) slice 32 ~ ~ cfh c0h ffh f8h f7h f0h fh 8h 7h 0h slice 1 10h set 1 only 0 0 0 0 0 x x x figure 2- 7 . 8-byte working register areas (slices)
address spaces s3c8639/c863a/p863a /c8647/f8647 2- 10 using the register pointers register pointers of rp0 and rp1 which are mapped to the addresses d6h and d7h in set 1, are used to select two movable 8 -byte working register slices in the register file. after a reset, they point to the wo rking register common area: rp0 points to the addresses c0h ? c7h, and rp1 points to the addresses c8h ? cfh. you can change a register pointer value, by load ing a new value to rp0 and/or rp1 using an srp or ld instruction (see figures 2-6 and 2-7). in working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by rp0 and rp1. you cannot use the register pointers to select a working register area in set 2, c0h? ffh, because these locations can be accessed only with indirect register or indexed addressing modes. the 16-byte working register block selected usually consists of two contiguous 8-byte slices. as a general programming guideline, we recommend that rp0 point to the "lower" slice and rp1 point to the "upper" slice (see figure 2-6). in some cases, it may be necessary to define working register areas in different (non-contiguous) areas of the register file. in figure 2-7, rp0 points to the "upper" slice and rp1 to the "lower" slice. as a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly define the working register area to support a variety of program requirements. f f programming tip ? setting the register pointers srp #70h ; rp0 ? 70h, rp1 ? 78h srp1 #48h ; rp0 ? no change, rp1 ? 48h srp0 #0a0h ; rp0 ? a0h, rp1 ? no change clr rp0 ; rp0 ? 00h, rp1 ? no change ld rp1,#0f8h ; rp0 ? no change, rp1 ? 0f8h fh (r15) 0h (r0) 16-byte contiguous working register block register file contains 32 8-byte slices rp0 rp1 8h 7h 0 0 0 0 1 x x x 0 0 0 0 0 x x x 8-byte slice 8-byte slice figure 2- 8 . contiguous 16-byte working register block
s3c8639/c863a/p863a/c8647/f8647 address spaces 2- 11 16-byte non- contiguous working register block register file contains 32 8-byte slices 0h (r0) 7h (r15) f0h (r0) f7h (r7) rp1 rp0 1 1 1 1 0 x x x 0 0 0 0 0 x x x 8-byte slice 8-byte slice figure 2- 9 . non-contiguous 16-byte working register block f f programming tip ? calculate the sum of a series of registers using the rps calculate the sum of registers 80h ? 85h using the register pointer and working register addressing. the register addresses from 80h through 85h contain the values 10h, 11h, 12h, 13h, 14h, and 15h, respectively: srp0 #80h ; rp0 ? 80h add r0,r1 ; r0 ? r0 + r1 adc r0,r2 ; r0 ? r0 + r2 + c adc r0,r3 ; r0 ? r0 + r3 + c adc r0,r4 ; r0 ? r0 + r4 + c adc r0,r5 ; r0 ? r0 + r5 + c the sum of these six registers, 6fh, is located in the register r0 (80h). the instruction string used in this example takes 12 bytes of instruction code and its execution time is 24 cycles. if the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used: add 80h,81h ; 80h ? (80h) + (81h) adc 80h,82h ; 80h ? (80h) + (82h) + c adc 80h,83h ; 80h ? (80h) + (83h) + c adc 80h,84h ; 80h ? (80h) + (84h) + c adc 80h,85h ; 80h ? (80h) + (85h) + c t he sum of the six registers , here, is also located in the register 80h. t his instruction string , h owever, takes 15 bytes of instruction code instead of 12 bytes, and its execution time is 3 0 cycles instead of 24 cycles.
address spaces s3c8639/c863a/p863a /c8647/f8647 2- 12 register addressing the sam8 register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. with register (r) addressing mode, in which the operand value is the content of a specific register or register pair, you can access all locations in the register file except for set 2. with working register addressing, you use a register pointer to specify an 8 -byte working register space in the register file and an 8-bit register within that space. registers are addressed either as a single 8-bit register or as a paired 16-bit register space. in a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+1) odd-numbered register. working register addressing differs from register addressing in a way that it uses a register pointer to specify an 8 -byte working register space in the register file and an 8-bit register within that space (see figure 3-2). msb rn lsb rn+1 n = even address figure 2- 10 . 16-bit register pair
s3c8639/c863a/p863a/c8647/f8647 address spaces 2- 13 ffh d0h ffh c0h set 2 cfh d7h rp1 d6h rp0 register pointers c0h bfh 00h general-purpose registers each register pointer (rp) can independently point to one of the 24 8-byte "slices" of the register file (other than set 2). after a reset, rp0 points to locations c0h-c7h and rp1 to locations c8h-cfh (the common working register area). special-purpose registers set 1 bank 1 bank 0 control registers system registers e0h (s3c863a: page 0, 1, 2, 3 s3c8639: page 0, 1, 2 s3c8647: page 0, 1) all addressing modes page 0, 1, 2, 3 indirect register, indexed addressing modes register addressing only can be pointed to by register pointer page 0, 1, 2, 3 figure 2- 11 . register file addressing
address spaces s3c8639/c863a/p863a /c8647/f8647 2- 14 common working register area (c0h ? cfh) after a reset, register pointers rp0 and rp1 automatically select two 8-byte register slices in set 1, locations c0h?cfh, as the active 16-byte working register block: rp0 ? c0h ? c7h rp1 ? c8h ?c fh this16-byte address range is called common working register area . that is, locations in this area can be used as working registers by operations that address any location on any page in the register file. typically, these working registers serve as temporary buffers for data operations between different pages. prime area page 3 ~ set 2 prime area page 2 ~ set 2 ~ prime area page 1 ~ set 2 ffh fch e0h dfh cfh c0h set 1 rp0 = 1 1 0 0 0 0 0 0 rp1 = 1 1 0 0 1 0 0 0 register pointers rp0 and rp1 point to the common working register area, locations c0h-cfh, after a reset. ffh c0h bfh 00h ffh c0h bfh 00h page 0 set 2 prime area ~ ~ (s3c863a only) figure 2- 12 . common working register area (s3c863x)
s3c8639/c863a/p863a/c8647/f8647 address spaces 2- 15 page 1 ffh fch e0h dfh cfh c0h set 1 rp0 = 1 1 0 0 0 0 0 0 rp1 = 1 1 0 0 1 0 0 0 register pointers rp0 and rp1 point to the common working register area, locations c0h-cfh, after a reset. ffh c0h bfh 00h page 0 set 2 prime area ~ ~ prime area 7fh 00h figure 2-1 3 . common working register area (s3c8647)
address spaces s3c8639/c863a/p863a /c8647/f8647 2- 16 f f programming tip ? addressing the common working register area as the following examples show, you should access working registers in the common area, locations c0h ? cfh, using working register addressing mode only. example s: 1 . ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: srp #0c0h ld r2,40h ; r2 (c2h) ? the value in location 40h 2. add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: srp #0c0h add r3,#45h ; r3 (c3h) ? r3 + 45h
s3c8639/c863a/p863a/c8647/f8647 address spaces 2- 17 4 -bit working register addressing each register pointer defines a movable 8-byte slice of working register space. the address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. when an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: ? the high-order bit of the 4-bit address sel ects one of the register pointers ("0" selects rp0; "1" selects rp1); ? the five high-order bits in the register pointer select an 8-byte slice of the register space; ? the three low-order bits of the 4-bit address select one of the eight registers in the slice. as shown in figure 2-11, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. as long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. figure 2-12 shows a typical example of 4-bit working register addressing: t he high-order bit of the instruction " inc r6 " is "0", which selects rp0. the five high-order bits stored in rp0 (01110b) are concatenated with the three low-order bits of the instruction's 4-bit address (110b) to produce the register address 76h (01110110b). together they create an 8-bit register address register pointer provides five high-order bits address opcode selects rp0 or rp1 rp1 rp0 4-bit address provides three low-order bits figure 2- 14 . 4-bit working register addressing
address spaces s3c8639/c863a/p863a /c8647/f8647 2- 18 register address (76h) rp0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 r6 0 1 1 0 1 1 1 0 selects rp0 instruction 'inc r6' opcode rp1 0 1 1 1 1 0 0 0 figure 2-1 5 . 4-bit working register addressing example
s3c8639/c863a/p863a/c8647/f8647 address spaces 2- 19 8-bit working register addressing you can also use 8-bit working register addressing to access registers in a selected working register area. to initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value of 1100b. this 4-bit value (1100b) indicates that the remaining four bits have the same effect as 4-bit working register addressing. as shown in figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4 -bit addressing: bit 3 selects either rp0 or rp1, which then supplies the five high-order bits of the final address; the three low-order bits of the complete address are provided by the original instruction. figure 2-14 shows an example of 8-bit working register addressing: t he four high-order bits of the instruction address (1100b) specify 8-bit working register addressing. bit 4 ("1") selects rp1 and the five high-order bits in rp1 (10101b) become the five high-order bits of the register address. the three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. the five address bits from rp1 and the three address bits from the instruction are concatenated to form the complete register address, 0abh (10101011b). 8-bit logical address 8-bit physical address register pointer provides five high-order bits address selects rp0 or rp1 rp1 rp0 three low-order bits these address bits indicate 8-bit working register addressing 1 1 0 0 figure 2- 16 . 8-bit working register addressing
address spaces s3c8639/c863a/p863a /c8647/f8647 2- 20 8-bit address form instruction 'ld r11, r2' rp0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 selects rp1 r11 register address (0abh) rp1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 specifies working register addressing figure 2-1 7 . 8-bit working register addressing example
s3c8639/c863a/p863a/c8647/f8647 address spaces 2- 21 system and user stacks s 3 -series microcontrollers can be programmed to use the system stack for subroutine calls, returns and interrupts and to store data. the push and pop instructions are used to control system stack operations. the s3c8639/c863a architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls and interrupts and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address is always decremented before a push operation and incremented after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2-15. stack contents after a call instruction stack contents after an interrupt top of stack flags pch pcl pcl pch top of stack low address high address figure 2- 18 . stack operations user-defined stacks you can freely define stacks in the internal register file as data storage locations. the instructions pushui, pushud, popui, and popud support user-defined stack operations. stack pointers (spl, sph) register locations d8h and d9h contain the 16-bit stack pointer (sp) that is used for system stack operations. the most significant byte of the sp address, sp15?sp8, is stored in the sph register (d8h) and the least significant byte, sp7?sp0, is stored in the spl register (d9h). after a reset, the sp value is undetermined. because only internal memory space is implemented in s3c8639/c863a , the spl must be initialized to an 8-bit value in the range 00h?ffh . t he sph register is not needed here and can be used as a general-purpose register, if necessary. when the spl register contains the only stack pointer value (that is, when it points to a system stack in the register file), you can use the sph register as a general-purpose data register. however, if an overflow or underflow condition occurs as the result of incrementing or decrementing the stack address in the spl register during normal stack operations, the value in the spl register will overflow (or underflow) to the sph register, overwriting any data that is currently stored there. to avoid overwriting data in the sph register, you can initialize the spl value to " ffh " rather than " 00h " .
address spaces s3c8639/c863a/p863a /c8647/f8647 2- 22 f f programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld spl,#0 ffh ; spl ? ffh ; (normally, the spl is set to 0ffh by the initialization ; routine) push pp ; stack address 0feh ? pp push rp0 ; stack address 0fdh ? rp0 push rp1 ; stack address 0fch ? rp1 push r3 ; stack address 0fbh ? r3 pop r3 ; r3 ? stack address 0fbh pop rp1 ; rp1 ? stack address 0fch pop rp0 ; rp0 ? stack address 0fdh pop pp ; pp ? stack address 0feh
s3c8639/c863a/p863a/c8647/f8647 addressing modes 3- 1 3 addressing modes overview the program counter is used to fetch instructions that are stored in program memory for execution. instructions indicate the operation to be performed and the data to be operated on. addressing mode is used to determine the location of the data operand. the operands specified in sam8 instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the sam8 instruction set supports seven explicit addressing modes. not all of these addressing modes are available for each instruction: ? register (r) ? indirect register (ir) ? indexed (x) ? direct address (da) ? indirect address (ia) ? relative address (ra) ? immediate (im)
addressing modes s3c8639/c863a/p863a/c8647/f8647 3- 2 register addressing mode (r) in register addressing mode, the operand is the content of a specified register or register pair (see figure 3-1). working register addressing differs from register addressing as it uses a register pointer to specify an 8 -byte working register space in the register file and an 8-bit register within that space (see figure 3-2). dst value used in instruction execution opcode operand 8-bit register file address point to one rigister in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address program memory register file figure 3-1. register addressing dst opcode 4-bit working register point to the woking register (1 of 8) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 and r2 are registers in the working register area currently selected program memory register file src 3 lsbs rp0 or rp1 selected rp points to start of working register block operand msb point to rp0 of rp1 figure 3-2. working register addressing
s3c8639/c863a/p863a/c8647/f8647 addressing modes 3- 3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space, if implemented (see figures 3-3 through 3-6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. remember, however, that locations c0h?ffh in set 1 cannot be accessed using indirect register addressing mode. dst address of operand used by instruction opcode address 8-bit register file address point to one rigister in register file one-operand instruction (example) sample instruction: rl @shift ; where shift is the label of an 8-bit register address program memory register file value used in instruction execution operand figure 3-3. indirect register addressing to register file
addressing modes s3c8639/c863a/p863a/c8647/f8647 3- 4 indirect register addressing mode (c ontinued ) dst opcode points to rigister pair example instruction references program memory sample instructions: call @rr2 jp @rr2 program memory register file value used in instruction operand register pair program memory 16-bit address points to program memory figure 3-4. indirect register addressing to program memory
s3c8639/c863a/p863a/c8647/f8647 addressing modes 3- 5 indirect register addressing mode (c ontinued ) dst opcode address 4-bit working register address point to the working register (1 of 8) sample instruction: or r3,@r6 program memory register file src 3 lsbs value used in instruction operand selected rp points to start of woking register block rp0 or rp1 msb points to rp0 or rp1 ~ ~ ~ ~ figure 3-5. indirect working register addressing to register file
addressing modes s3c8639/c863a/p863a/c8647/f8647 3- 6 indirect register addressing mode (c oncluded ) dst opcode 4-bit working register address sample instructions: lcd r5,@rr6 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4,r8 ; external data memory access program memory register file src value used in instruction operand example instruction references either program memory or data memory program memory or data memory next 2-bit point to working register pair (1 of 4) lsb selects register pair 16-bit address points to program memory or data memory rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block figure 3-6. indirect working register addressing to program or data memory
s3c8639/c863a/p863a/c8647/f8647 addressing modes 3- 7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3-7). you can use indexed addressing mode to access locations in the internal register file or in external memory (if implemented). you cannot, however, access locations c0h?ffh in set 1 using indexed addressing. in short offset indexed addressing mode, the 8 -bit displacement is treated as a signed integer in the range from ? 128 to +127. this applies to external memory accesses only (see figure 3-8) . for register file addressing, an 8 -bit base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory access, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to the base address (see figure 3-9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory and for external data memory (if implemented). dst/src opcode two-operand instruction example point to one of the woking register (1 of 8) sample instruction: ld r0,#base[r1] ; where base is an 8-bit immediate value program memory register file x 3 lsbs value used in instruction operand index base address rp0 or rp1 selected rp points to start of working register block ~ ~ ~ ~ + msb points to rp0 to rp1 figure 3-7. indexed addressing to register file
addressing modes s3c8639/c863a/p863a/c8647/f8647 3- 8 indexed addressing mode (c ontinued ) register file operand program memory or data memory point to working register pair (1 of 4) lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block dst/src opcode program memory x offset 4-bit working register address sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + 04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 8-bits 16-bits 16-bits + ~ ~ figure 3-8. indexed addressing to program or data memory with short offset
s3c8639/c863a/p863a/c8647/f8647 addressing modes 3- 9 indexed addressing mode (c oncluded ) register file operand program memory or data memory point to working register pair lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block sample instructions: ldc r4,#1000h[rr2] ; the values in the program address (rr2 + 1000h) are loaded into register r4. lde r4,#1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 8-bits 16-bits 16-bits dst/src opcode program memory src offset 4-bit working register address offset + ~ ~ figure 3-9. indexed addressing to program or data memory
addressing modes s3c8639/c863a/p863a/c8647/f8647 3- 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. dst/src opcode program memory "0" or "1" lower address byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper address byte program or data memory figure 3-10. direct addressing for load instructions
s3c8639/c863a/p863a/c8647/f8647 addressing modes 3- 11 direct address mode (c ontinued) opcode program memory upper address byte program memory address used lower address byte sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address next opcode figure 3-11. direct addressing for call and jump instructions
addressing modes s3c8639/c863a/p863a/c8647/f8647 3- 12 indirect address mode (ia) in indirect address (ia) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. the selected pair of memory locations contains the actual address of the next instruction to be executed. only the call instruction can use indirect address mode. because indirect address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction . t he upper bytes of the destination address are assumed to be all zeros. current instruction program memory locations 0-255 program memory opcode dst lower address byte upper address byte next instruction lsb must be zero sample instruction: call #40h ; the 16-bit value in program memory addresses 40h and 41h is the subroutine start address. figure 3-12. indirect addressing
s3c8639/c863a/p863a/c8647/f8647 addressing modes 3- 13 relative address mode (ra) in relative address (ra) mode, a two's-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the next instruction immediately following the current instruction. several program control instructions use the relative address mode to perform conditional jumps. the instructions that support ra addressing are btjrf, btjrt, djnz, cpije, cpijne, and jr. opcode program memory displacement program memory address used sample instruction: jr ult,$+offset ; where offset is a value in the range +127 to -128 next opcode + signed displacement value current instruction current pc value figure 3-13. relative addressing
addressing modes s3c8639/c863a/p863a/c8647/f8647 3- 14 immediate mode (im) in immediate (im) mode, the operand value used in the instruction is the value supplied in the operand field itself. the operand may be one byte or one word in length, depending on the instruction used. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) opcode sample instruction: ld r0,#0aah program memory operand figure 3-14. immediate addressing
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 1 4 control registers overview in this chapter, detailed descriptions of the s3c8639/c863a/c8647 control registers are presented in an easy-to- read format. you can use this chapter as a quick-reference source when writing application programs. the locations and read/write characteristics of all mapped registers in the s3c8639/c863a/c8647 register files are presented in tables 4-1, 4-2, and 4-3. the hardware reset values for these registers are described in chapter 8, " reset and power-down." figure 4-1 illustrates the important features of the standard register description format. control register descriptions are arranged in alphabetical order according to register mnemonic. more detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in part ii of this manual.
control registers s3c8639/c863a/p863a/c8647/f8647 4- 2 table 4-1. set 1 registers register name mnemonic decimal hex r/w timer m0 counter register tm0cnt 208 d0h r (note) timer m0 data register tm0data 209 d1h r (note) timer m0 control register tm0con 210 d2h r/w basic timer control register btcon 211 d3h r/w clock control register clkcon 212 d4h r/w system flags register flags 213 d5h r/w register pointer 0 rp0 214 d6h r/w register pointer 1 rp1 215 d7h r/w stack pointer (high byte) sph 216 d8h r/w stack pointer (low byte) spl 217 d9h r/w instruction pointer (high byte) iph 218 dah r/w instruction pointer (low byte) ipl 219 dbh r/w interrupt request register irq 220 dch r (note) interrupt mask register imr 221 ddh r/w system mode register sym 222 deh r/w page pointer register pp 223 dfh r/w note: you cannot use a read-only register (tm0cnt, tm0data, irq) as a destination field for the instructions or, and, ld, or ldb.
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 3 table 4-2. set 1, bank 0 registers register name mnemonic decimal hex r/w port 0 data register p0 224 e0h r/w port 1 data register (2) p1 225 e1h r/w port 2 data register p2 226 e2h r/w port 3 data register p3 227 e3h r/w port 0 control register (high byte) p0conh 228 e4h r/w port 0 control register (low byte) p0conl 229 e5h r/w port 1 control register (2) p1con 230 e6h r/w port 2 control register (high byte) p2conh 231 e7h r/w port 2 control register (low byte) p2conl 232 e8h r/w port 3 control register (high byte) p3conh 233 e9h r/w port 3 control register (low byte) p3conl 234 eah r/w port 0 external interrupt control register p0int 235 ebh r/w watchdog time control register wdtcon 236 ech r/w sync control register 0 syncon0 237 edh r/w sync control register 1 syncon1 238 eeh r/w sync control register 2 syncon2 239 efh r/w sync port read data register syncrd 240 f0h r (1) timer m1 counter register (high byte) tm1cnth 241 f1h r (1) timer m1 counter register (low byte) tm1cntl 242 f2h r (1) timer m1 data register (high byte) tm1datah 243 f3h r (1) timer m1 data register (low byte) tm1datal 244 f4h r (1) timer m1 control register tm1con 245 f5h r/w timer m2 control register tm2con 246 f6h r /w a/d converter control register adcon 247 f7h r /w a/d converter data register addata 248 f8h r (1) pseudo hsync generation register phgen 249 f9h r /w pseudo vsync generation register pvgen 250 fah r /w stop control register stopcon 251 fbh r /w location fch is not mapped basic timer counter register btcnt 253 fdh r (1) external memory timing register emt 254 feh r/w interrupt priority register ipr 255 ffh r/w notes: 1. you cannot use a read-only register (syncrd, tm1cnth, tm1tncl, tm1datah, tm1datal, addata, btcnt) as a destination field for the instructions or, and, ld, or ldb. 2. not used for the s3c8647.
control registers s3c8639/c863a/p863a/c8647/f8647 4- 4 table 4-3. set 1, bank 1 registers register name mnemonic decimal hex r/w pwm 0 data register pwm0 224 e0h r/w pwm 1 data register pwm1 225 e1h r/w pwm 2 data register pwm2 226 e2h r/w pwm 3 data register pwm3 227 e3h r/w pwm 4 data register pwm4 228 e4h r/w pwm 5 data register pwm5 229 e5h r/w pwm 6 data register (2) pwm6 230 e6h r/w pwm control register pwmcon 231 e7h r/w pwm counter register pwmcnt 232 e8h r (1) ddc control register dcon 233 e9h r/w ddc address register 0 dar0 234 eah r/w ddc clock control register dccr 235 ebh r/w ddc control/status register 0 dcsr0 236 ech r/w ddc control/status register 1 dcsr1 237 edh r/w ddc address register 1 dar1 238 eeh r/w transmit prebuffer data register tbdr 239 efh r/w receive prebuffer data register rbdr 240 f0h r (1) ddc data shift register ddsr 241 f1h r/w slave iic-bus control/status register (2) sicsr 243 f2h r/w slave iic-bus address register (2) siar 242 f3h r/w slave iic-bus data shift register (2) sidsr 244 f4h r/w locations f5h?ffh are not mapped notes : 1. you cannot use a read-only register (pwmcnt, rbdr) as a destination field for the instructions or, and, ld, or ldb. 2. not used for the s3c8647.
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 5 flags - system flags register .7 carry flag (c) .6 zero flag (z) .5 bit identifier reset value read/write bit addressing mode r = read-only w = write-only r/w = read/write '-' = not used type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) reset value notation: '-' = not used 'x' = undetermined value '0' = logic zero '1' = logic one bit number(s) that is/are appended to the register name for bit addressing name of individual bit or related bits register name register id sign flag (s) 0 operation does not generate a carry or borrow condition 0 operation generates carry-out or borrow into high-order bit 7 0 operation result is a non-zero value 0 operation result is zero 0 operation generates positive number (msb = "0") 0 operation generates negative number (msb = "1") description of the effect of specific bit settings set 1 register location in the internal register file d5h register address (hexadecimal) .7 .6 .5 x x x r/w r/w r/w register addressing mode only .4 .3 .2 .1 .0 x r/w x r/w x r/w x r/w 0 r/w bit number: msb = bit 7 lsb = bit 0 figure 4-1. register description format
control registers s3c8639/c863a/p863a/c8647/f8647 4- 6 adcon ? a/d converter control register f7h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? 0 0 0 0 0 0 0 read/write ? r/w r/w r/w r r/w r/w r/w addressing mode register addressing mode only .7 not used for the s3c8639/c863a/c8647 .6 and .4 analog input pin selection bits 0 0 0 adc0 (port 3.0) 0 0 1 adc1 (port 3.1) 0 1 0 adc2 (port 3.2) 0 1 1 adc3 (port 3.3) others not used .3 end-of conversion (eoc) flag (read-only) 0 conversion not complete 1 conversion is complete .2 and .1 clock source selection bits 0 0 f osc /16 0 1 f osc /8 1 0 f osc /4 1 1 f osc .0 start or enable bit 0 disable operation 1 start operation
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 7 btcon ? basic timer control register d3h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 watchdog timer function disable bits 1 0 1 0 disable watchdog timer function others enable watchdog timer function .3 and .2 basic timer input clock selection bits 0 0 f osc /4096 0 1 f osc /1024 1 0 f osc /128 1 1 invalid setting; not used for the s3c8639/c863a/c8647 .1 basic timer counter clear bit (1) 0 no effect 1 clear the basic timer counter value .0 clock frequency divider clear bit for basic timer and timer m0 (2) 0 no effect 1 clear basic timer and timer m0 frequency dividers notes: 1. when you write a ?1? to btcon.1, the basic timer counter value is cleared to "00h". immediately after the write operation, the btcon.1 value is automatically cleared to ?0?. 2. when you write a "1" to btcon.0, the corresponding frequency divider is cleared to "00h". immediately after the write oper ation, the btcon.0 value is automatically cleared to "0".
control registers s3c8639/c863a/p863a/c8647/f8647 4- 8 clkcon ? system clock control register d4h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 oscillator irq wake-up function enable bit 0 enable irq for main system oscillator wake-up in power-down mode 1 disable irq for main system oscillator wake-up in power-down mode .6 and .5 main oscillator stop control bits 0 0 no effect 0 1 no effect 1 0 stop main oscillator 1 1 no effect .4 and .3 cpu clock (system clock) selection bits (1) 0 0 divide by 16 (f osc /16) 0 1 divide by 8 (f osc /8) 1 0 divide by 2 (f osc /2) 1 1 non-divided clock (f osc ) (2) .2?.0 subsystem clock selection bits (3) 1 0 1 invalid setting for s3c8639/c863a/c8647 others select main system clock (mclk) notes: 1. after a reset, the slowest clock (divided by 16) is selected as the system clock. to select faster clock speeds, load the appropriate values to clkcon.3 and clkcon.4. 2. if the oscillator frequency is higher than 12 mhz, this selection is invalid. 3. these selection bits are required only for systems that have a main clock and a subsystem clock. s3c8639/c863a/c8647 use only the main oscillator clock circuit. for this reason, the setting "101b" is invalid.
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 9 dar0 ? ddc address register 0 eah set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 0 1 0 ? ? ? ? read/write r/w r/w r/w r/w ? ? ? ? addressing mode register addressing mode only .7?.4 4-slave address bits these bits are operate only when receive the slave address. read enable anytime. write enable when dcsr0.4 is "0". .3?.0 not used for the s3c8639/c863a/c8647 dar1 ? ddc address register 1 eeh set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x ? read/write r/w r/w r/w r/w r/w r/w r/w ? addressing mode register addressing mode only .7?.1 7-slave address bits these bits are operate only when receive the slave address. read enable anytime. write enable when dcsr0.4 is "0". .0 not used for the s3c8639/c863a/c8647
control registers s3c8639/c863a/p863a/c8647/f8647 4- 10 dccr ? ddc clock control register ebh set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 transmit acknowledgement enable mode when this bit is "1". .6 tx clock selection bit 0 f osc /10 1 f osc /256 .5 ddc module interrupt enable bit 0 disable interrupt 1 enable interrupt .4 ddc module interrupt pending bit 0 when write "0" to this bit (write "1" has no effect) 0 when dcsr0.4 is "0" 1 when slave address match occurred 1 when arbitration lost (master mode) 1 when an 1-byte transmit or receive operation is terminated 1 as soon as the ddc1 mode is enabled after the prebuffer is used .3?.0 transmit clock 4-bit prescaler bits (ccr3?ccr0) scl clock = iiclk/(ccr < 3: 0 > +1) where, iiclk is f osc /10 when dccr.6 is "0" iiclk is f osc /256 when dccr.6 is "1"
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 11 dcon ? ddc control register e9h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 1 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 not used for the s3c8639/c863a/c8647. .3 tx/rx pre-buffer data registers enable bit 0 normal iic-bus mode (pre-buffer data registers are not used.) 1 pre-buffer data registers enable mode. this bit is set by writing "1" or by a reset. .2 ddc address match bit 0 when start or stop or reset 1 when ddc received address matchs to dar0 register .1 ddc1 tx mode enable bit 0 iic-bus interface mode (scl pin is also selected) 1 ddc1 tx mode (vclk pin is also selected) .0 scl pin falling edge detection flag (note) 0 scl pin level remains high after a reset (when read) 0 this bit can be cleared by s/w written "0" (when write) 1 falling edge can be detected at the scl pin after a reset or after this flag is cleared by software (when read) after start condition, the clock source of ddc module automatically charges from vclk (vsync-i) to scl0 (dcon.1 is "1" to "0") and slave address match possible. 1 no effect (when write) note: when ddc interrupt is occurred, the scl line is not pull-down in the ddc1 mode and tx/rx pre-buffer data registers enable bit, dcon.3 is "1" (only slave mode).
control registers s3c8639/c863a/p863a/c8647/f8647 4- 12 dcsr0 ? ddc control/status register 0 ech set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 ? 0 read/write r/w r/w r/w r/w r r ? r addressing mode register addressing mode only .7?.6 master/slave, tx/rx mode selection bits 0 0 slave receiver mode (default mode) 0 1 slave transmitter mode 1 0 master receiver mode 1 1 master transmitter mode .5 bus busy bit 0 iic-bus is not busy (when read), stop condition generation (when write) 1 iic-bus is busy (when read), start condition generation (when write) .4 ddc module enable bit 0 disable ddc module 1 enable ddc module .3 arbitration lost bit 0 bus arbitration status okay 1 bus arbitration failed during serial i/o .2 ddc address/data classification bit 0 when reset or start/stop condition is generated, or when the received data is in the data field. 1 when the received slave address matchs to dar0, dar1 register .1 not used for the s3c8639/c863a/c8647 .0 received acknowledgement (ack) bit 0 ack is received 1 ack is not received note: bits 3?0 are read only.
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 13 dcsr1 ? ddc control/status register 1 edh set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? 0 1 0 read/write ? ? ? ? ? r/w r/w r/w addressing mode register addressing mode only .7?.3 not used for the s3c8639/c863a/c8647 .2 stop condition detection bit 0 when it writes "0" to this bit, it is reset or master mode. 1 when a stop condition is detected after start and slave address reception .1 data buffer empty status bit 0 when the cpu writes the transmitted data into the tbdr register 1 when the data of the tbdr register is loads to the ddsr register or when a stop condition is detected in dcsr0.7-.6 (slave transmitter mode) = "01" .0 data buffer full status bit 0 when the cpu reads the received data from the rbdr register or stop condition 1 when the data or matched address is transferred from the ddsr register to the rbdr register
control registers s3c8639/c863a/p863a/c8647/f8647 4- 14 ddsr ? ddc data shift register f1h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 write enable when dcsr0.4 is "1" and dcon.3 is "0". read enable anytime.
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 15 emt ? external memory timing register feh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 1 1 1 1 1 0 ? read/write r/w r/w r/w r/w r/w r/w r/w ? addressing mode register addressing mode only .7 external wait input function enable bit 0 disable wait input function for external device 1 enable wait input function for external device .6 slow memory timing enable bit 0 disable slow memory timing 1 enable slow memory timing .5 and .4 program memory automatic wait control bits 0 0 no wait (normal operation) 0 1 wait one cycle 1 0 wait two cycles 1 1 wait three cycles .3 and .2 data memory automatic wait control bits 0 0 no wait (normal operation) 0 1 wait one cycle 1 0 wait two cycles 1 1 wait three cycles .1 stack area selection bit 0 select internal register file area 1 select external data memory area .0 not used for the s3c8639/c863a/c8647 note : a s external peripheral interface is not implemented in s3c8639/c863a/c8647, emt register is not used. the program initialization routine should clear the emt register to "00h" after a reset. modification of emt values during the normal operation may cause a system malfunction.
control registers s3c8639/c863a/p863a/c8647/f8647 4- 16 flags ? system flags register d5h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 carry flag (c) 0 operation does not generate a carry or borrow condition 1 operation generates a carry-out or borrow into high-order bit 7 .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is +127 or 3 ?128 1 operation result is > +127 or < ?128 .3 decimal adjust flag (d) 0 add operation completed 1 subtraction operation completed .2 half-carry flag (h) 0 no carry-out of bit 3 or no borrow into bit 3 by addition or subtraction 1 addition generated carry-out of bit 3 or subtraction generated borrow into bit 3 .1 fast interrupt status flag (fis) 0 cleared automatically during an interrupt return (iret) 1 automatically set to logic one during a fast interrupt service routine .0 bank address selection flag (ba) 0 bank 0 is selected (by executing the instruction sb0) 1 bank 1 is selected (by executing the instruction sb1)
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 17 imr ? interrupt mask register ddh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 interrupt level 7 (irq7) enable bit; slave only iic-bus interrupt (only s3c863x) 0 disable irq7 interrupt 1 enable irq7 interrupt .6 interrupt level 6 (irq6) enable bit; p0.2 external interrupt (int2) 0 disable irq6 interrupt 1 enable irq6 interrupt .5 interrupt level 5 (irq5) enable bit; p0.1 external interrupt (int1) 0 disable irq5 interrupt 1 enable irq5 interrupt .4 interrupt level 4 (irq4) enable bit; p0.0 external interrupt (int0) 0 disable irq4 interrupt 1 enable irq4 interrupt .3 interrupt level 3 (irq3) enable bit; ddc (multi-master iic-bus) interrupt 0 disable irq3 interrupt 1 enable irq3 interrupt .2 interrupt level 2 (irq2) enable bit; timer m1 capture/overflow interrupt 0 disable irq2 interrupt 1 enable irq2 interrupt .1 interrupt level 1 (irq1) enable bit; timer m2 interval interrupt 0 disable irq1 interrupt 1 enable irq1 interrupt .0 interrupt level 0 (irq0) enable bit; timer m0 overflow/capture interrupt 0 disable irq0 interrupt 1 enable irq0 interrupt
control registers s3c8639/c863a/p863a/c8647/f8647 4- 18 iph ? instruction pointer (high byte) dah set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 instruction pointer address (high byte) the high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (ip15?ip8). the lower byte of the ip address is located in the ipl register (dbh). ipl ? instruction pointer (low byte) dbh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 instruction pointer address (low byte) the low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (ip7?ip0). the upper byte of the ip address is located in the iph register (dah).
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 19 ipr ? interrupt priority register ffh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7, .4 and .1 priority control bits for interrupt groups a, b and c 0 0 0 not used 0 0 1 b > c > a 0 1 0 a > b > c 0 1 1 b > a > c 1 0 0 c > a > b 1 0 1 c > b > a 1 1 0 a > c > b 1 1 1 not used .6 interrupt sub-group c priority control bit 0 irq6 > irq7 1 irq7 > irq6 .5 interrupt group c priority control bit 0 irq5 > (irq6, irq7) 1 (irq6, irq7) > irq5 .3 interrupt sub-group b priority control bit 0 irq3 > irq4 1 irq4 > irq3 .2 interrupt group b priority control bit 0 irq2 > (irq3, irq4) 1 (irq3, irq4) > irq2 .0 interrupt group a priority control bit 0 irq0 > irq1 1 irq1 > irq0 note: interrupt group a is irq0 and irq1. interrupt group b is irq2, irq3, and irq4. interrupt group c is irq5, irq6 and irq7.
control registers s3c8639/c863a/p863a/c8647/f8647 4- 20 irq ? interrupt request register dch set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r r r r r r r r addressing mode register addressing mode only .7 level 7 (irq7) request pending bit; slave only iic-bus interrupt (only s3c863x) 0 no irq7 interrupt pending 1 irq7 interrupt is pending .6 level 6 (irq6) request pending bit; p0.2 external interrupt (int2) 0 no irq6 interrupt pending 1 irq6 interrupt is pending .5 level 5 (irq5) request pending bit; p0.1 external interrupt (int1) 0 no irq5 interrupt pending 1 irq5 interrupt is pending .4 level 4 (irq4) request pending bit; p0.0 external interrupt (int0) 0 no irq4 interrupt pending 1 irq4 interrupt is pending .3 level 3 (irq3) request pending bit; ddc (multi-master iic-bus) interrupt 0 no irq3 interrupt pending 1 irq3 interrupt is pending .2 level 2 (irq2) request pending bit; timer m1 capture/overflow interrupt 0 no irq2 interrupt pending 1 irq2 interrupt is pending .1 level 1 (irq1) request pending bit; timer m2 interval interrupt 0 no irq1 interrupt pending 1 irq1 interrupt is pending .0 level 0 (irq0) request pending bit; timer m0 overflow/capture interrupt 0 no irq0 interrupt pending 1 irq0 interrupt is pending
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 21 p0conh ? port 0 control register (high byte) e4h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 p0.7 mode selection bits (not used for s3c8647) 0 x input mode 1 x push-pull output mode .5 and .4 p0.6 mode selection bits (not used for s3c8647) 0 x input mode 1 x push-pull output mode .3 and .2 p0.5 mode selection bits (not used for s3c8647) 0 x input mode 1 x push-pull output mode .1 and .0 p0.4/tm0cap mode selection bits 0 0 input mode 0 1 tm0cap input mode 1 x push-pull output mode
control registers s3c8639/c863a/p863a/c8647/f8647 4- 22 p0conl ? port 0 control register (low byte) e5h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 p0.3 mode selection bits (not used for s3c8647) 0 0 input mode 0 1 input mode 1 0 input mode 1 1 push-pull output mode .5 and .4 p0.2/int2 mode selection bits 0 0 input mode (p0.2) 0 1 input mode, rising edge interrupt detection (int2) 1 0 input mode, falling edge interrupt detection (int2) 1 1 push-pull output mode .3 and .2 p0.1/int1 mode selection bits 0 0 input mode (p0.1) 0 1 input mode, rising edge interrupt detection (int1) 1 0 input mode, falling edge interrupt detection (int1) 1 1 push-pull output mode .1 and .0 p0.0/int0 mode selection bits 0 0 input mode (p0.0) 0 1 input mode, rising edge interrupt detection (int0) 1 0 input mode, falling edge interrupt detection (int0) 1 1 push-pull output mode
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 23 p0int ? port 0 external interrupt control register ebh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? 0 0 0 ? 0 0 0 read/write ? r/w r/w r/w ? r/w r/w r/w addressing mode register addressing mode only .7 and .3 not used for the s3c8639/c863a/c8647 .6 p0.2 external interrupt (int2, irq6) pending flag (note) 0 no p0.2 external interrupt pending (when read) 0 clear p0.2 interrupt pending condition (when write) 1 p0.2 external interrupt is pending (when read) .5 p0.1 external interrupt (int1, irq5) pending flag 0 no p0.1 external interrupt pending (when read) 0 clear p0.1 interrupt pending condition (when write) 1 p0.1 external interrupt is pending (when read) .4 p0.0 external interrupt (int0, irq4) pending flag 0 no p0.0 external interrupt pending (when read) 0 clear p0.0 interrupt pending condition (when write) 1 p0.0 external interrupt is pending (when read) .2 p0.2 external interrupt (int2, irq6) enable bit 0 disable p0.2 interrupt 1 enable p0.2 interrupt .1 p0.1 external interrupt (int1, irq5) enable bit 0 disable p0.1 interrupt 1 enable p0.1 interrupt .0 p0.0 external interrupt (int0, irq4) enable bit 0 disable p0.0 interrupt 1 enable p0.0 interrupt note: writing a "1" to an interrupt pending flag (p0.2, p0.1, p0.0) has no effect.
control registers s3c8639/c863a/p863a/c8647/f8647 4- 24 p1con ? port 1 control register (only s3c863x) e6h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 not used for the s3c8639/c863a/c8647 .5 and .4 p1.2 mode selection bits 0 0 input mode 0 1 push-pull output mode 1 0 n-channel open-drain output mode (5 v load capability) 1 1 not used .3 and .2 p1.1/scl1 mode selection bits 0 0 input mode 0 1 push-pull output mode 1 0 n-channel open-drain output mode (5 v load capability) 1 1 multiplexed mode (scl1 (p1.1)) .1 and .0 p1.0/sda1 mode selection bits 0 0 input mode 0 1 push-pull output mode 1 0 n-channel open-drain output mode (5 v load capability) 1 1 multiplexed mode (sda1 (p1.0))
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 25 p2conh ? port 2 control register (high byte) e7h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 p2.7/csync-i 0 x ttl input mode (csync-i) 1 x push-pull output mode .5 and .4 p2.6/pwm6 mode selection bits (not used for s3c8647) 0 0 input mode 0 1 push-pull output mode 1 0 push-pull pwm output mode 1 1 n-channel open-drain pwm output mode (5 v load capability) .3 and .2 p2.5/pwm5 mode selection bits 0 0 input mode 0 1 push-pull output mode 1 0 push-pull pwm output mode 1 1 n-channel open-drain pwm output mode (5 v load capability) .1 and .0 p2.4/pwm4 mode selection bits 0 0 input mode 0 1 push-pull output mode 1 0 push-pull pwm output mode 1 1 n-channel open-drain pwm output mode (5 v load capability)
control registers s3c8639/c863a/p863a/c8647/f8647 4- 26 p2conl ? port 2 control register (low byte) e8h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 p2.3/pwm3 mode selection bits 0 x input mode 1 0 push-pull output mode 1 1 push-pull pwm output mode (5 v load capability) .5 and .4 p2.2/pwm2 mode selection bits 0 x input mode 1 0 push-pull output mode 1 1 push-pull pwm output mode (5 v load capability) .3 and .2 p2.1/pwm1 mode selection bits 0 x input mode 1 0 push-pull output mode 1 1 push-pull pwm output mode (5 v load capability) .1 and .0 p2.0/pwm0 mode selection bits 0 x input mode 1 0 push-pull output mode 1 1 push-pull pwm output mode (5 v load capability)
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 27 p3conh ? port 3 control register (high byte) e9h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 p3.7 mode selection bits 0 0 input mode 0 1 input mode with pull-up resistor 1 0 push-pull output mode 1 1 n-channel open-drain output mode .5 and .4 p3.6 mode selection bits 0 0 input mode 0 1 input mode with pull-up resistor 1 0 push-pull output mode 1 1 n-channel open-drain output mode .3 and .2 p3.5 mode selection bits 0 0 input mode 0 1 input mode with pull-up resistor 1 0 push-pull output mode 1 1 n-channel open-drain output mode .1 and .0 p3.4 mode selection bits 0 0 input mode 0 1 input mode with pull-up resistor 1 0 push-pull output mode 1 1 n-channel open-drain output mode
control registers s3c8639/c863a/p863a/c8647/f8647 4- 28 p3conl ? port 3 control register (low byte) eah set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 p3.3/ad3 mode selection bits 0 0 input mode 0 1 analog input mode (ad3) 1 0 push-pull output mode 1 1 n-channel open-drain output mode .5 and .4 p3.2/ad2 mode selection bits 0 0 input mode 0 1 analog input mode (ad2) 1 0 push-pull output mode 1 1 n-channel open-drain output mode .3 and .2 p3.1/ad1 mode selection bits 0 0 input mode 0 1 analog input mode (ad1) 1 0 push-pull output mode 1 1 n-channel open-drain output mode .1 and .0 p3.0/ad0 mode selection bits 0 0 input mode 0 1 analog input mode (ad0) 1 0 push-pull output mode 1 1 n-channel open-drain output mode
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 29 phgen ? pseudo hsync generation register f9h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 1 0 1 0 0 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 write enable when syncon2.4 is "0". (general pseudo h/vsync generation mode) read enable any time
control registers s3c8639/c863a/p863a/c8647/f8647 4- 30 pp ? page pointer register dfh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 destination register page selection bits 0 0 0 0 destination: page 0 0 0 0 1 destination: page 1 0 0 1 0 destination: page 2 (not used for the s3c8647) 0 0 1 1 destination: page 3 (not used for the s3c8639) 0 1 0 0 not used for the s3c8639/c863a/c8647 1 1 1 1 not used for the s3c8639/c863a/c8647 .3?.0 source register page selection bits 0 0 0 0 source: page 0 0 0 0 1 source: page 1 0 0 1 0 source: page 2 (not used for the s3c8647) 0 0 1 1 source: page 3 (not used for the s3c8639) 0 1 0 0 not used for the s3c8639/c863a/c8647 1 1 1 1 not used for the s3c8639/c863a/c8647
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 31 pvgen ? pseudo vsync generation register fah set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 1 0 1 0 0 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 write enable syncon2.4 is "0". (general pseudo h/vsync generation mode) read enable any time
control registers s3c8639/c863a/p863a/c8647/f8647 4- 32 pwmcon ? pwm control register e7h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 ? ? ? ? ? read/write r/w r/w r/w ? ? ? ? ? addressing mode register addressing mode only .7 and .6 2-bit prescaler value for pwm counter input clock 0 0 non-divided input clock 0 1 input clock divided into two 1 0 input clock divided into three 1 1 input clock divided into four .5 pwm counter enable bit 0 stop pwm counter operation (no current leakage) 1 start (or resume) pwm counter operation .4?.0 not used for the s3c8639/c863a/c8647
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 33 rbdr ? receive pre-buffer data register f0h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r r r r r r r r addressing mode register addressing mode only .7?.0 it is a read-only register. read enable anytime. this register will be updated after a data byte is received when the dcsr0.2 is "1" and the dcsr1.0 will be "1". the read operation of this register will clear the dcsr1.0. after the dcsr1.0 is cleared, the register can load the received data again and set the dcsr1.0.
control registers s3c8639/c863a/p863a/c8647/f8647 4- 34 rp0 ? register pointer 0 d6h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 1 0 0 0 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing only .7?.3 register pointer 0 address value register pointer 0 can independently point to one of the 18 8-byte working register areas in the register file. using the register pointers, rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp0 points to address c0h in register set 1, selecting the 8-byte working register slice c0h?c7h. .2?.0 not used for the s3c8639/c863a/c8647 rp1 ? register pointer 1 d7h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 1 0 0 1 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing only .7?.3 register pointer 1 address value register pointer 1 can independently point to one of the 18 8-byte working register areas in the register file. using the register pointers, rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp1 points to address c8h in register set 1, selecting the 8-byte working register slice c8h?cfh. .2?.0 not used for the s3c8639/c863a/c8647
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 35 siar ? slave iic-bus address register (only s3c863x) f3h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x ? read/write r/w r/w r/w r/w r/w r/w r/w ? addressing mode register addressing only .7?.1 7-bit slave address bits these bits are operated only when receive the slave address and general call. write enable when sicsr.6 is "0", but read enable anytime. .0 not used for the s3c8639/c863a/c8647
control registers s3c8639/c863a/p863a/c8647/f8647 4- 36 sicsr ? slave iic-bus control/status register (only s3c863x) f2h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r r r addressing mode register addressing mode only .7 acknowledgement enable bit 0 disable ack generation 1 enable ack generation .6 slave iic-bus module enable bit 0 disable iic-bus module 1 enable iic-bus module (enable serial data tx/rx) .5 slave iic-bus tx/rx interrupt enable bit 0 disable interrupt 1 enable interrupt .4 slave iic-bus tx/rx interrupt pending bit 0 no interrupt pending (when read) clear pending condition (when write) 0 when sicsr.6 is "0" 1 when 1-byte tx/rx is terminated 1 when slave address match occurred .3 slave iic-bus tx/rx mode status bit 0 slave receive mode (default mode) 1 slave transmitter mode .2 iic-bus busy status bit 0 iic-bus is not busy 1 iic-bus is busy .1 slave address match bit 0 when start or stop or reset 1 when received slave address matchs to siar register .0 received acknowledge (ack) bit 0 ack is received 1 ack is not received note: bit 2-0 are read only.
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 37 sidsr ? slave iic-bus tx/rx data shift register (only s3c863x) f4h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing only .7?.0 slave iic-bus transmit/receive data shift bus write enable when sicsr.6 is "1", but read enable anytime.
control registers s3c8639/c863a/p863a/c8647/f8647 4- 38 sph ? stack pointer (high byte) d8h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 stack pointer address (high byte) the high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (sp15?sp8). the lower byte of the stack pointer value is located in the register spl (d9h). the sp value is undefined after a reset. spl ? stack pointer (low byte) d9h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 stack pointer address (low byte) the low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer address (sp7?sp0). the upper byte of the stack pointer value is located in the register sph (d8h). the sp value is undefined after a reset.
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 39 stopcon ? stop control register fbh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 stop operation enable bits 1 0 1 0 0 1 0 1 enable the stop (power saving) function others disable the stop function notes: 1. if you intend to stop function for power saving, before stop op-code, you must set this register value to a5h (10100101b). 2. when stop mode is released, stop control register (stopcon) value is cleared automatically.
control registers s3c8639/c863a/p863a/c8647/f8647 4- 40 sym ? system mode register deh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 ? ? x x x 0 0 read/write r/w ? ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 tri-state external interface control bit (1) 0 normal operation (disable tri-state operation) 1 set external interface lines to high impedance (enable tri-state operation) .6 and .5 not used for the s3c8639/c863a/c8647 .4?.2 fast interrupt level selection bits (2) 0 0 0 irq0 0 0 1 irq1 0 1 0 irq2 0 1 1 irq3 1 0 0 irq4 1 0 1 irq5 1 1 0 irq6 1 1 1 irq7 (not used for the s3c8647) .1 fast interrupt enable bit (3) 0 disable fast interrupt processing 1 enable fast interrupt processing .0 global interrupt enable bit (4) 0 disable global interrupt processing 1 enable global interrupt processing notes: 1. as external interface is not implemented in s3c8639/c863a/c8647, sym.7 must always be "0". 2. you can select only one interrupt level at a time for fast interrupt processing. 3. setting sym.1 to "1" enables fast inte rrupt processing for the interrupt level currently selected by sym.2?sym.4. 4. after a reset, you must enable global interrupt processing by executing an ei instruction (not by writing a "1" to sym.0).
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 41 syncon0 ? sync processor control register 0 edh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r r r r r addressing mode register addressing mode only .7 sync input selection (sis) bit 0 hsync-i input is selected 1 csync-i input is selected .6 hsync blanking enable bit 0 disable (hsync signal by-pass) (when syncon0.5 = "0") 1 enable hsync blanking automatically (during the vsync signal extraction period) (when syncon0.5 = "1") .5 vsync-o output selection (vos) bit 0 select vsync-i port input (when separate sync input mode) 1 select 5-bit compare output (when composite sync input mode) .4?.0 5-bit counter value bits 5-bit counter increases when a high level is detected, while an overflow dose not occur (stop at "11111"). it decreases when a low level is detected, while an underflow does not occur (stop at "00000") when syncon0.5 is "1": sync separation and output (when counter value increases to "11111", output the high through the mux and when counter value decreases to "00000", output becomes low. resume the previous status when "11111" > counter value > "00000")
control registers s3c8639/c863a/p863a/c8647/f8647 4- 42 syncon1 ? sync processor control register 1 eeh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r r addressing mode register addressing mode only .7 and .6 clamp signal generator selection bits 0 0 inhibit clamp signal output (clamp-o) 0 1 (f osc 2) clock pulse output (250 ns at 8 mhz f osc ) 1 0 (f osc 4) clock pulse output (500 ns at 8 mhz f osc , 333 ns at 12 mhz f osc ) 1 1 (f osc 8) clock pulse output (1 m s at 8 mhz f osc , 666ns at 12 mhz f osc ) .5 "front porch"/"back porch" mode selection bit 0 generate clamp-o after the rising edge of hsync ("front porch" mode) 1 generate clamp-o after the falling edge of hsync ("back porch" mode) .4 clamp signal output status control bit (cosc) 0 negative polarity 1 positive polarity .3 vsync-o status control bit 0 do not invert (by-pass) 1 invert output signal .2 hsync-o status control bit (hosc) 0 do not invert (by-pass) 1 invert output signal .1 vsync polarity detection bit (1) 0 negative polarity 1 positive polarity .0 hsync polarity detection bit (2) 0 negative polarity 1 positive polarity notes: 1. to check hsync/vsync polarity, it uses 16 clocks of timer m2 (f osc /1000). if the vsync polarity is changing, this bit will be updated after a typical delay of 2 ms, at 8 mhz f osc (1.33 ms at 12 mhz f osc ). 2. the syncon1.0 may not be accurate when the hsync-i is composite-sync signal output. .
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 43 syncon2 ? sync processor control register 2 efh set 1, bank 0 bit identifier .7 ? .5 .4 .3 .2 .1 .0 reset reset value 0 ? 0 0 0 0 0 0 read/write r/w ? r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 unmixed hsync detection bit (when syncon0.5 is "1") 0 mixed hsync period with vsync of a composite sync input (this bit still cleared before being read this bit or it is been in mixed hsync period) 1 unmixed hsync periods .6 not used for the s3c8639/c863a/c8647(only ?0?) .5 5-bit counter source clock (fsync) input selection bit (1) 0 f osc /3 (when f cpu is 12 mhz) 1 f osc /2 (when f cpu is 8 mhz) .4 pseudo sync generation disable bit (positive polarity only) 0 enable pseudo hsync/vsync generation 1 normal sync-processor operation (by-pass) .3 sync signal output disable bit 0 enable sync signal output 1 inhibit sync signal output (output level is low) .2 sog (sync on green) detection bit 0 no sog signal (when read) 0 clear sog detection 6-bit counter (when write) 1 csync-i is sog signal (2) .1 5-bit up/down counter latch status changing detection bit 0 when the latch status is not changed or it writes"0" to this bit 1 when the latch status changing is detected. .0 v dd level selection bit for ttl sync-input port (not used for the s3c8647) 0 when v dd is +5 v 1 when v dd is +3 v notes: 1. countable maximum hsync pulse width = 7.85 us (when fsync is 4 mhz) 2. to check sog presence, it uses 64 csync-i input edge signal. 3. the syncon2.1 can be used to check the presence of composite-sync signal input.
control registers s3c8639/c863a/p863a/c8647/f8647 4- 44 syncrd ? sync processor port read data register f0h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r r r r addressing mode register addressing mode only .7?.4 not used for the s3c8639/c863a/c8647 .3 vertical sync signal output data bit (vsync-o) 0 low data 1 high data .2 horizontal sync signal output data bit (hsync-o) 0 low data 1 high data .1 vertical sync signal input data bit (vsync-i) 0 low data 1 high data .0 horizontal sync signal input data bit (hsync-i) 0 low data 1 high data
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 45 tbdr ? transmit pre-buffer data register efh set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 write enable when dcsr0.4 is "1", read enable anytime when dcon.3 (tbdr enable bit) = "1" and dcsr1.1 = "0", the data written into his register will be automatically downloaded to the ddc data shift register (ddsr) and generate the interrupt request when the module detects the calling address is matched and the bit 0 of the received data is "1" (dcsr0.7-6 = "01") and when the data in the ddsr register has been transmitted with received acknowledge bit, dcsr0.0 = "0". at this interrupt service routine, the cpu must write the next data to the tbdr register to clear dcsr1.1 and for the auto downloading of data to the ddsr register after the data in the ddsr register is transmitted over again with dcsr0.0 = "0".when dcon.3 = "1" and ddsr1.1 = "1", the data stored in this register will not be downloaded to the ddsr register and generated the interrupt request when the module detects the calling address is matched and the bit 0 of the received data is "1". at this interrupt service routine, the cpu must write the current data and rewrite the next data to the tbdr register to clear dcsr1.1. if the master receiver doesn?t acknowledge the transmitted data, dcsr0.0 = "1", the module will release the sda line for master to generate stop or repeated start conditions. if dcon.3 (tbdr enable bit) is "0", the module will pull-down the scl line in the iic-bus interrupt service routine when the dcsr0.2 is "1". and the module will release the scl line if the cpu writes a data to the ddsr registers and the interrupt pending bit is cleared.
control registers s3c8639/c863a/p863a/c8647/f8647 4- 46 tm0con ? timer m0 control register d2h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 timer m0 input clock selection bit 0 f osc /128 1 f osc /8 .6 and .5 2 bit prescaler bits 0 0 no division 0 1 divided by 2 1 0 divided by 3 1 1 divided by 4 .4 timer m0 capture mode selection bit 0 capture on rising mode 1 capture on falling mode .3 timer m0 counter clear bit (tm0clr) 0 no effect 1 clear timer m0 counter, tm0cnt (when write) .2 timer m0 overflow interrupt enable bit (tm0ovint) (1) 0 disable timer m0 overflow interrupt 1 enable timer m0 overflow interrupt .1 timer m0 capture interrupt enable bit (tm0int) 0 disable timer m0 interrupt (2) 1 enable timer m0 interrupt .0 timer m0 capture input selection bit (tm0capsel) 0 tm0cap input pin selection 1 vsync output path selection from sync-processor notes: 1. when the captured value is #0ffh, the overflow interrupt does not occurred. if the captured value is changed from #0ffh to #00h, the overflow interrupt occurs. when the captured value is #00h, the overflow interrupt occurs first. 2. when the timer m0 interrupt is disabled, the timer m0 overflow interrupt by f osc can happen .
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 47 tm1con ? timer m1 control register f5h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 capture signal source selection bit 0 signal from timer m2 interval time 1 vsync-o from sync-processor .6 vsync-o capture egde selection bit (when tm1con.7 = "1") 0 capture vsync-o (from sync-processor) on rising edge 1 capture vsync-o (from sync-processor) on falling edge .5 timer m1 capture interrupt enable bit (tm1int) 0 disable timer m1 capture 1 enable timer m1 capture .4 timer m1 capture pending bit (tm1pnd) 0 interrupt is not pending (when read) 0 clear this pending bit (when write) 1 interrupt is pending (when read) 1 no effect (when write) .3 timer m1 counter clear bit (tm1clr; when write) 0 no effect 1 clear timer m1 counter .2 timer m1 overflow interrupt enable bit (tm1ovf) 0 disable timer m1 overflow interrupt 1 enable timer m1 overflow interrupt .1?.0 timer m1 clock input selection bit 0 0 hsync-i or csync-i from sync processor 0 1 f osc /2 1 0 f osc /128 1 1 f osc /512
control registers s3c8639/c863a/p863a/c8647/f8647 4- 48 tm2con ? timer m2 control register f6h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 1 1 1 1 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.3 5-bit prescale bits (tm2ps4?tm2ps0) 0 0 0 0 0 no division 0 0 0 0 1 divide by 2 0 0 0 1 0 divide by 3 1 1 1 1 1 divide by 32 .2 timer m2 interrupt enable bit (tm2int) 0 disable timer m2 interrupt 1 enable timer m2 interrupt .1 and .0 timer m2 capture interval time selection bits (when tm2con.5 is "1") 0 0 timer m2 interval (by pass) 0 1 timer m2 interval 10 1 0 timer m2 interval 20 1 1 timer m2 interval 30 notes: 1. when the timer m1 capture mode is enabled (tm1con.5 = "1"), the value of 5/2-bit prescaler is changed only in the timer m1 capture interrupt routine. 2. when the timer m1 capture mode is disabled (tm1con.5 = "0"), the value of 5-bit prescaler is changed only in the timer m2 interval inte rrupt routine.
s3c8639/c863a/p863a/c8647/f8647 control registers 4- 49 wdtcon ? watchdog time control register ech set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 not used for the s3c8639/c863a/c8647 .3 hsync-o divide enable bit 0 hsync-o = hsync-i (non-divide) 1 hsync-o = hsync-i/2 .2?.0 watchdog time generation control bits 0 0 0 tbtovf (note) 0 0 1 tbtovf/2 0 1 0 tbtovf/3 0 1 1 tbtovf/4 1 0 0 tbtovf/5 1 0 1 tbtovf/6 1 1 0 tbtovf/7 1 1 1 tbtovf/8 note: tbtovf = (1/f osc ) (divider count of basic timer input clock) 256
control registers s3c8639/c863a/p863a/c8647/f8647 4- 50 notes
s3c8639/c863a/p863a/c8647/f8647 interrupt structure 5- 1 5 interrupt structure overview the sam8 interrupt structure has three basic components: levels, vectors, and sources. the cpu recognizes eight interrupt levels and supports up to 128 interrupt vectors. when a specific interrupt level has more than one vector address, the vector priorities are established in hardware. each vector can have one or more sources. levels interrupt levels are the main unit for interrupt priority assignment and recognition. all peripherals and i/o blocks can issue interrupt requests. in other words, peripheral and i/o operations are interrupt-driven. there are eight interrupt levels: irq0?irq7, also called level 0?level 7. each interrupt level directly corresponds to an interrupt request number (irqn). the total number of interrupt levels used in the interrupt structure varies from device to device. the interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. they are just identifiers for the interrupt levels that are recognized by the cpu. the relative priority of different interrupt levels is determined by settings in the interrupt priority register, ipr. interrupt group and subgroup logic controlled by ipr settings lets you define more complex priority relationships between different levels. vectors each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. the maximum number of vectors that can be supported for a given level is 128. (the actual number of vectors used for s3c8-series devices will always be much smaller.) if an interrupt level has more than one vector address, the vector priorities are set in hardware. s3c8639/c863a/c8647* have ten (nine)* vectors ? one corresponding to each of the ten (nine)* possible interrupt sources. sources a source is any peripheral that generates an interrupt. a source can be an external pin or a counter overflow. each vector can have several interrupt sources. in the s3c8639/c863a/c8647* interrupt structure, each source has its own vector address. when a service routine starts, the respective pending bit should be either cleared automatically by hardware or cleared "manually" by program software. the characteristics of the source's pending mechanism determine which method would be used to clear its respective pending bit.
interrupt structure s3c8639/c863a/p863a/c8647/f8647 5- 2 interrupt types the three components of the sam8 interrupt structure described before ? levels, vectors, and sources ? are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. there are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. the types differ in the number of vectors and interrupt sources assigned to each level (see figure 5-1): type 1: one level (irqn) + one vector (v 1 ) + one source (s 1 ) type 2: one level (irqn) + one vector (v 1 ) + multiple sources (s 1 ? s n ) type 3: one level (irqn) + multiple vectors (v 1 ? v n ) + multiple sources (s 1 ? s n , s n+1 ? s n+m ) in the s3c8639/c863a/c8647 microcontrollers, only interrupt types 1 and 3 are implemented. vectors sources levels s 1 v 1 s 2 type 2: irqn s 3 s n v 1 s 1 v 2 s 2 type 3: irqn v 3 s 3 v 1 s 1 type 1: irqn v n s n + 1 s n s n + 2 s n + m notes: 1. the number of s n and v n value is expandable. 2. in the s3c8639/c863a/c8647 implementation, interrupt types 1 and 3 are used. figure 5-1. s3c8-series interrupt types
s3c8639/c863a/p863a/c8647/f8647 interrupt structure 5- 3 s3c8639/c863a/c8647 interrupt structure the s3c8639/c863a/c8647 microcontrollers support ten interrupt sources. each interrupt source has a corresponding interrupt vector address. all eight interrupt levels are used in the device-specific interrupt structure, which is shown in figure 5-2. when multiple interrupt levels are active, the interrupt priority register (ipr) determines the order in which contending interrupts are to be serviced. if multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first. (the relative priorities of multiple interrupts within a single level are fixed in hardware.) when the cpu grants an interrupt request, interrupt processing starts: all other interrupts are disabled and the program counter value and status flags are pushed to stack. the starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed. vectors sources levels timer m2 interval interrupt irq1 timer m1 overflow interrupt timer m1 capture interrupt irq2 ddc (multi-master iic-bus) interrupt p0.0 external interrupt (int0) irq4 p0.1 external interrupt (int1) p0.2 external interrupt (int2) slave only iic-bus interrupt (note) timer m0 overflow interrupt irq0 timer m0 capture interrupt reset/clear h/w h/w s/w s/w s/w s/w s/w s/w h/w h/w irq3 irq5 irq6 irq7 e4h e6h e8h eah ech eeh f0h f2h e0h e2h note: not used for the s3c8647. figure 5-2. s3c8639/c863a/c8647 interrupt structure
interrupt structure s3c8639/c863a/p863a/c8647/f8647 5- 4 interrupt vector addresses all interrupt vector addresses for the s3c8639/c863a/c8647 interrupt structure are stored in the vector address area of the rom, 00h ?ffh (see figure 5-3). you can allocate unused locations in the vector address area as normal program memory. if you do so, please be careful not to overwrite any of the stored vector addresses. (table 5-1 lists all vector addresses.) the program reset address in the rom is 0100h. 49,151 0 (decimal) 255 interrupt vector addressarea 32/48-kbyte addressable pregram memory (rom) area (s3c863x) 33,767 0h 0100h 0ffh bfffh (hex) 7fffh reset address 8000h 24,535 5fffh 24-kbyte addressable pregram memory (rom) area (s3c8647) figure 5-3. rom vector address area
s3c8639/c863a/p863a/c8647/f8647 interrupt structure 5- 5 table 5-1. s3c8639/c863a/c8647 interrupt vectors vector address request reset/clear decimal value hex value interrupt source interrupt level priority in level h/w s/w 224 226 e0h e2h timer m0 overflow interrupt timer m0 capture interrupt irq0 0 1 ? ? 228 e4h timer m2 interval interrupt irq1 ? ? 230 232 e6h e8h timer m1 overflow interrupt timer m1 capture interrupt irq2 0 1 ? ? 234 eah ddc (multi-master iic-bus) interrupt irq3 ? ? 236 ech p0.0 external interrupt (int0) irq4 ? ? 238 eeh p0.1 external interrupt (int1) irq5 ? ? 240 f0h p0.2 external interrupt (int2) irq6 ? ? 242 f2h slave only iic-bus interrupt (3) irq7 ? ? notes : 1. interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on. 2. if two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority over one with a higher vector address. the priorities within a given level are fixed in hardware. 3. not used for the s3c8647.
interrupt structure s3c8639/c863a/p863a/c8647/f8647 5- 6 enable/disable interrupt instructions (ei, di) executing the enable interrupts (ei) instruction enables the interrupt structure. all interrupts are then serviced as they occur according to the established priorities. note the system initialization routine executed after a reset must always contain an ei instruction (assuming one or more interrupts are used in the application). during the normal operation, you can execute the di (disable interrupt) instruction at any time to globally disable interrupt processing. the ei and di instructions change the value of bit 0 in the sym register. although you can directly manipulate sym.0 to enable or disable interrupts, it is recommended that you use the ei and di instructions instead. system-level interrupt control registers in addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing: ? the interrupt mask register, imr, enables (un-masks) or disables (masks) interrupt levels. ? the interrupt priority register, ipr, controls the relative priorities of interrupt levels. ? the interru pt request register, irq, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source). ? the system mode register, sym, enables or disables global interrupt processing. (sym settings also enable fast interrupts and control the activity of external interface, if implemented.) table 5-2. interrupt control register overview control register id r/w function description interrupt mask register imr r/w bit settings in the imr register enable or disable interrupt processing for each of the eight interrupt levels, irq0?irq7. interrupt priority register ipr r/w controls the relative processing priorities of the interrupt levels. the eight levels are organized into three groups: a, b, and c. group a is irq0 and irq1, group b is irq2?irq4, and group c is irq5?irq7. interrupt request register irq r this register contains a request pending bit for each of the seven interrupt levels, irq0?irq7. system mode register sym r/w this register enables and disables dynamic global interrupt processing and fast interrupt processing.
s3c8639/c863a/p863a/c8647/f8647 interrupt structure 5- 7 interrupt processing control points interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. among the system-level control points in the interrupt structure are: ? global interrupt enabled and disabled (by ei and di instructions or by direct manipulation of sym.0 ) ? interrupt level enable/disable sett ings (imr register) ? interrupt level priority settings (ipr register) ? interrupt source enable/disable settings in the corresponding peripheral control registers note when writing an application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information. source interrupts s r q reset "ei" instruction execution source interrupts enable interrupt pending register (read-only) polling cycle interrupt request register (read-only) global interrupt control (ei, di instruction) interrupt priority register global interrupt control (ei, di or sym.0 manipulation) vector interrupt cycle figure 5-4. interrupt function diagram
interrupt structure s3c8639/c863a/p863a/c8647/f8647 5- 8 peripheral interrupt control registers for each interrupt source there is a corresponding peripheral control register (or registers) controlling the interrupts generated by the related peripheral. these registers and their locations are listed in table 5-3. table 5-3. interrupt source control registers interrupt source interrupt level control register(s) register location(s) timer m0 overflow interrupt timer m0 capture interrupt irq0 tm0con set 1, d2h timer m2 interval interrupt irq1 tm2con set 1, bank 0, f6h timer m1 overflow interrupt timer m1 capture interrupt irq2 tm1con set 1, bank 0, f5h ddc (multi-master iic-bus) interrupt irq3 dccr dcsr0 set 1, bank 1, ebh set 1, bank 1, ech p0.0 external interrupt irq4 p0conl p0int set 1, bank 0, e5h set 1, bank 0, ebh p0.1 external interrupt irq5 p0conl p0int set 1, bank 0, e5h set 1, bank 0, ebh p0.2 external interrupt irq6 p0conl p0int set 1, bank 0, e5h set 1, bank 0, ebh slave only iic-bus interrupt (note) irq7 sicsr set 1, bank 1, f2h note: not used for the s3c8647.
s3c8639/c863a/p863a/c8647/f8647 interrupt structure 5- 9 system mode register (sym) the system mode register, sym (set 1, deh), is used to globally enable and disable interrupt processing and to control fast interrupt processing. figure 5-5 shows the effect of the various control settings. a reset clears sym.7, sym.1, and sym.0 to "0". other sym bit values (for fast interrupt level selection) are undetermined. the instructions ei and di enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the sym register. in order to enable interrupt processing an enable interrupt (ei) instruction must be included in the initialization routine, which follows a reset operation. although you can manipulate sym.0 directly to enable and disable interrupts during the normal operation, it is recommended to use the ei and di instructions for this purpose. note: not used for the s3c8647. system mode register (sym) deh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb global interrupt enable bit: 0 = disable all interrupts 1 = enable all interrupts fast interrupt enable bit: 0 = disable fast interrupts 1 = enable fast interrupts not used for s3c8639/c863a/c8647 external interface tri-state enable bit: 0 = normal operation (tri-state disabled) 1 = high impedance (tri-state enabled) fast interrupt level selection bits: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 irq0 irq1 irq2 irq3 irq4 irq5 irq6 irq7 (note) figure 5-5. system mode register (sym)
interrupt structure s3c8639/c863a/p863a/c8647/f8647 5- 10 interrupt mask register (imr) the interrupt mask register, imr (set 1, ddh) is used to enable or disable interrupt processing for individual interrupt levels. after a reset, all imr bit values are undetermined and must therefore be written to their required settings by the initialization routine. each imr bit corresponds to a specific interrupt level: bit 1 to irq1, bit 2 to irq2, and so on. when the imr bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). when you set a level's imr bit to "1", interrupt processing for the level is enabled (not masked). the imr register is mapped to register location ddh in set 1. bit values can be read and written by instructions using the register addressing mode. interrupt mask register (imr) ddh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb irq1 irq2 irq3 irq4 irq5 irq6 irq7 (note) irq0 interrupt level enable bits (7-0): 0 = disable (mask) interrupt level 1 = enable (un-mask)interrupt level note: not used for the s3c8647. figure 5-6. interrupt mask register (imr)
s3c8639/c863a/p863a/c8647/f8647 interrupt structure 5- 11 interrupt priority register (ipr) the interrupt priority register, ipr (set 1, bank 0, ffh), is used to set the relative priorities of the interrupt levels in the microcontroller?s interrupt structure. after a reset, all ipr bit values are undetermined and must therefore be written to their required settings by the initialization routine. when more than one interrupt sources are active, the source with the highest priority is serviced first. if two sources belong to the same interrupt level, the source with the lower vector address usually has priority. (this priority is fixed in hardware.) to support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. please note that these groups (and subgroups) are used only by ipr logic for the ipr register priority definitions (see figure 5-7): group a irq0, irq1 group b irq2, irq3, irq4 group c irq5, irq6, irq7 ipr group a irq1 a2 irq0 a1 irq2 b1 irq4 b2 ipr group b irq3 irq5 c1 irq7 c2 ipr group c irq6 b21 b22 c21 c22 figure 5-7. interrupt request priority groups as you can see in figure 5-8, ipr.7, ipr.4, and ipr.1 control the relative priority of interrupt groups a, b, and c. for example, the setting "001b" for these bits would select the group relationship b > c > a. the setting "101b" would select the relationship c > b > a. the functions of the other ipr bit settings are as follows: ? interrupt group c includes a sub group that has an additional priority relationship among interrupt levels 5, 6, and 7. ipr.6 defines the subgroup c relationship. ? ipr.5 controls the relative priorities of group c interrupts. ? interrupt group b includes a subgroup that has an additional priority relationship among interrupt levels 2, 3, and 4. ipr.3 defines the subgroup b relationship. ? ipr.2 controls interrupt group b. ? ipr.0 controls the relative priority setting of irq0 and irq1 interrupts.
interrupt structure s3c8639/c863a/p863a/c8647/f8647 5- 12 interrupt priority register (ipr) ffh, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb group a 0 = irq0 > irq1 1 = irq1 > irq0 subgroup b 0 = irq3 > irq4 1 = irq4 > irq3 group c 0 = irq5 > (irq6, irq7) 1 = (irq6, irq7) > irq5 subgroup c 0 = irq6 > irq7 1 = irq7 > irq6 group b 0 = irq2 > (irq3, irq4) 1 = (irq3, irq4) > irq2 group priority: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 = not used = b > c > a = a > b > c = b > a > c = c > a > b = c > b > a = a > c > b = not used d7 d4 d1 figure 5-8. interrupt priority register (ipr)
s3c8639/c863a/p863a/c8647/f8647 interrupt structure 5- 13 interrupt request register (irq) you can poll bit values in the interrupt request register, irq (set 1, dch), to monitor interrupt request status for all levels in the microcontroller?s interrupt structure. each bit corresponds to the interrupt level of the same number: bit 0 to irq0, bit 1 to irq1, and so on. a "0" indicates that no interrupt request is currently being issued for that level. a "1" indicates that an interrupt request has been generated for that level. irq bit values are addressable in read-only using register addressing mode. you can read (test) the contents of the irq register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. after a reset, all irq status bits are cleared to ?0?. you can poll irq register values even if a di instruction has been executed (that is, if global interrupt processing is disabled). if an interrupt occurs while the interrupt structure is disabled, the cpu will not service it. you can, however, still detect the interrupt request by polling the irq register. in this way, you can determine which events occurred while the interrupt structure was globally disabled. interrupt request register (irq) dch, set 1, read-only .7 .6 .5 .4 .3 .2 .1 .0 msb lsb irq1 irq2 irq3 irq4 irq5 irq6 irq7 (note) irq0 interrupt level request pending bits: 0 = interrupt level is not pending 1 = interrupt level is pending note: not used for the s3c8647. figure 5-9. interrupt request register (irq)
interrupt structure s3c8639/c863a/p863a/c8647/f8647 5- 14 interrupt pending function types overview there are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared by the application program's interrupt service routine. pending bits cleared automatically by hardware for interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. it then issues an irq pulse to inform the cpu that an interrupt is waiting to be serviced. the cpu acknowledges the interrupt source, executes the service routine, and clears the pending bit to "0". this type of pending bit is not mapped and cannot, therefore, be read or written by application software. in the s3c8639/c863a/c8647 interrupt structure, the timer m0 overflow interrupt (irq0, vector e0h), the timer m0 capture interrupt (irq0, vector e2h), the timer m2 interval interrupt (irq1, vector e4h), and the timer m1 overflow interrupt (irq2, vector e6h) belong to this category of interrupts in which pending conditions are cleared automatically by hardware. pending bits cleared by the service routine the second type of pending bit is the one that should be cleared by program software. the service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (iret) occurs. to do this, a "0" must be written to the corresponding pending bit location in the source?s mode or control register. in the s3c8639/c863a/c8647 interrupt structure, pending conditions for all interrupt sources, except the timer m0 overflow/capture, the timer m2 interval interrupt and the timer m1 overflow interrupt, must be cleared by the program software's interrupt service routine.
s3c8639/c863a/p863a/c8647/f8647 interrupt structure 5- 15 interrupt source polling sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request bit to "1". 2. the cpu polling procedure identifies a pending condition for that source. 3. the cpu checks the source's interrupt level. 4. the cpu generates an interrupt acknowledge s ignal. 5. interrupt logic determines the interrupt's vector address. 6. the service routine starts and the source's pending bit is cleared to "0" (by hardware or by software). 7. the cpu continues polling for interrupt requests. interrupt service routines before an interrupt request is serviced, the following conditions must be met: ? interrupt processing must be globally enabled (ei, sym.0 = "1") ? the interrupt level must be enabled (imr register) ? the interrupt leve l must have the highest priority if more than one levels are currently requesting service ? the interrupt must be enabled at the interrupt's source (peripheral control register) when all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the interrupt enable bit in the sym register (sym.0) to disable all subsequent interrupts. 2. save the program counter (pc) and status flags to the system stack. 3. branch to the interrupt vector to fetch the address of the service routine. 4. pass control to the interrupt service routine. when the interrupt service routine is completed, the cpu issues an interrupt return (iret). the iret restores the pc and status flags, setting sym.0 to "1". it allows the cpu to process the next interrupt request.
interrupt structure s3c8639/c863a/p863a/c8647/f8647 5- 16 generating interrupt vector addresses the interrupt vector area in the rom (00h?ffh) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to the stack. 2. push the program counter's high-byte value to the stack. 3. push the flag register values to the stack. 4. fetch the service routine's high-byte address from the vector location. 5. fetch the service routine's low-byte address from the vector locatio n. 6. branch to the service routine specified by the concatenated 16-bit vector address. note a 16-bit vector address always begins at an even-numbered rom address within the range of 00h?ffh. nesting of vectored interrupts it is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. to do this, you must follow these steps: 1. push the current 8-bit interrupt mask register (imr) value to the stack (push imr). 2. load the imr register with a new mask value that enables only the higher priority interrupt. 3. execute an ei instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs). 4. when the lower-priority interrupt service routine ends, restore the imr to its original value by returning the previous mask value from the stack (pop imr). 5. execute an iret. depending on the application, you may be able to simplify the above procedure to some extent. instruction pointer (ip) the instruction pointer (ip) is adopted by all the s3c8-series microcontrollers to control the optional high-speed interrupt processing feature called fast interrupts . the ip consists of register pair dah and dbh. the names ip of registers are iph (high byte, ip15?ip8) and ipl (low byte, ip7?ip0).
s3c8639/c863a/p863a/c8647/f8647 interrupt structure 5- 17 fast interrupt processing the feature called fast interrupt processing allows an interrupt within a given level to be completed in approximately six clock cycles rather than the usual 10 clock cycles. sym.4?sym.2 are used to select a specific interrupt level for fast processing and sym.1 enables or disables fast interrupt processing. two other system registers support fast interrupt processing: ? the instruction pointer (ip) contains the starting address of the service routine (and is later used to swap the program counter values), and ? when a fast interrupt occurs, the contents of the flags register is stored in an unmapped, dedicated register called flags' ("flags prime"). notes 1. for the s3c8639/c863a/c8647 microcontrollers, the service routine for any of the seven interrupt levels (irq0?irq7) can be selected for fast interrupt processing. the s3c8647 microcontroller has six interrupt levels (irq0-irq6) for fast interrupt processing. 2. when you use a fast interrupt in a multi-source interrupt vector, the fast interrupt may not be processed if you use two sources as interrupt vector in normal mode. but it is possible when you use only one source as interrupt vector. procedure for initiating fast interrupts to initiate fast interrupt processing, follow these steps: 1. load the start address of the service routine into the instruction pointer (ip). 2. load the interrupt level number (irqn) into the fast interrupt selection field (sym.4?sym.2) 3. write a "1" to the fast interrupt enable bit in the sym register. fast interrupt service routine when an interrupt occurs in the level selected for fast interrupt processing, the following events occur: 1. the contents of the instruction pointer and the pc are swapped. 2. the flag register values are written to the flags' ("flags prime") register. 3. the fast interrupt status bit in the flags register is set. 4. the interrupt is serviced. 5. assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction pointer and pc values are swapped back. 6. the content of flags' ("flags prime") is copied automatically back to the flags register. 7. the fast interrupt status bit in flags is cleared automatically. relationship to interrupt pending bit types as described previously, there are two types of interrupt pending bits: one is the type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed, and the other is the one that must be cleared by the application program's interrupt service routine. you can select fast interrupt processing for interrupts with either type of pending condition clear function ? by hardware or by software.
interrupt structure s3c8639/c863a/p863a/c8647/f8647 5- 18 programming guidelines remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the sym register, sym.1. executing an ei or di instruction globally enables or disables all interrupt processing, including fast interrupts. note if you use fast interrupts, remember to load the ip with a new start address when the fast interrupt service routine ends. f f programming tip ? setting up the interrupt control structure this example shows you how to enable interrupts for select interrupt sources, disable interrupts for other sources, and set interrupt priorities for the s3c8639/c863a/c8647 interrupt structure. the following is a sample program: ? disables the watchdog function. ? enables the following interrupts: p0.0 external interrupt, timer m0 capture/overflow, timer m1 capture/overflow, timer m2 interval interrupt, and ddc interrupt. ? disables the following interrupts: p0.1 and p0.2 external interrupts, and slave only iic-bus interrupt. ? sets interrupt priorities as p0.0 > timer m2 > timer m0 > timer m1 > ddc. ? ? ? di ; disable interrupts globally ld btcon,#0a0h ; disable watchdog function ld p0conl,#01h ; p0.0 ? enable rising edge interrupts ld p0int,#01h ; enable p0.0 external interrupt ; disable p0.1 and p0.2 external interrupts ld tm0con,#8fh ; enable timer m0 capture interrupt ; (capture on rising edges) ; enable timer m0 overflow interrupt ld tm1con,#3ch ; enable timer m1 capture/overflow interrupt ld tm2con,#3dh ; enable timer m2 interval interrupt ld tm2data,#249 ; setting 1ms interval ld dccr,#0a3h ; enable ddc interrupt, scl clock = 100 khz ld imr,#1fh ; enable interrupt levels irq0, irq1, irq2, irq3 and ; irq4 ld ipr,#1eh ; irq4 > irq0 > irq1 > irq2 > irq3 ; (p0.0 > timer m0 > timer m2 > timer m1 > ddc) ei ; enable interrupts globally ? ? ?
s3c8639/c863a/p863a/c8647/f8647 interrupt structure 5- 19 f f programming tip ? programming level irq0 as a fast interrupt the following example shows you how to program fast interrupt processing for a selected interrupt level ? in this case, for the timer m0 capture interrupt: ? ? ? ld tm0con,#8fh ; enable tm0ovf interrupt ; enable tm0cap interrupt ; capture mode (on rising signal edges) ; select f osc /8 as the t0 clock source ld p0conh,#01h ; set p0.4 to capture input mode ldw iph,#t0_int ; iph ? high byte of interrupt service routine ; ipl ? low byte of interrupt service routine ld sym,#02h ; enable fast interrupt processing ; select irq0 for fast interrupt service ei ; enable interrupts ? ? ? fast_ret: iret ; ip ? address of t0_int (again) t0_int: ? ? ? (fast service routine executes) ? ? ? ld tm0con,#8fh ; clear tm0int interrupt pending bit jp t,fast_ret
interrupt structure s3c8639/c863a/p863a/c8647/f8647 5- 20 notes
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 1 6 instruction set overview the sam8rc instruction set is specifically designed to support the large register files that are typical of most sam8rc microcontrollers. there are 78 instructions. the powerful data manipulation capabilities and features of the instruction set include: ? a full complement of 8-bit arithmetic and logic operations, including multiply and divide ? no special i/o instructions (i/o control/data registers are mapped directly into the register file) ? decimal adjustment included in binary-coded decimal (bcd) operations ? 16-bit (word) data can be incremented and decremented ? flexible instructions for bit addressing, rotate, and shift operations data types the sam8rc cpu performs operations on bits, bytes, bcd digits, and two-byte words. bits in the register file can be set, cleared, complemented, and tested. bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit. register addressing to access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. paired registers can be used to construct 16-bit data or 16-bit program memory or data memory addresses. for detailed information about register addressing, please refer to section 2, "address spaces." addressing modes there are seven explicit addressing modes: register (r), indirect register (ir), indexed (x), direct (da), relative (ra), immediate (im), and indirect (ia). for detailed descriptions of these addressing modes, please refer to section 3, "addressing modes."
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 2 table 6-1. instruction group summary mnemonic operands instruction load instructions clr dst clear ld dst,src load ldb dst,src load bit lde dst,src load external data memory ldc dst,src load program memory lded dst,src load external data memory and decrement ldcd dst,src load program memory and decrement ldei dst,src load external data memory and increment ldci dst,src load program memory and increment ldepd dst,src load external data memory with pre-decrement ldcpd dst,src load program memory with pre-decrement ldepi dst,src load external data memory with pre-increment ldcpi dst,src load program memory with pre-increment ldw dst,src load word pop dst pop from stack popud dst,src pop user stack (decrementing) popui dst,src pop user stack (incrementing) push src push to stack pushud dst,src push user stack (decrementing) pushui dst,src push user stack (incrementing)
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 3 table 6-1. instruction group summary (cont inued ) mnemonic operands instruction arithmetic instructions adc dst,src add with carry add dst,src add cp dst,src compare da dst decimal adjust dec dst decrement decw dst decrement word div dst,src divide inc dst increment incw dst increment word mult dst,src multiply sbc dst,src subtract with carry sub dst,src subtract logic instructions and dst,src logical and com dst complement or dst,src logical or xor dst,src logical exclusive or
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 4 table 6-1. instruction group summary (cont inued ) mnemonic operands instruction program control instructions btjrf dst,src bit test and jump relative on false btjrt dst,src bit test and jump relative on true call dst call procedure cpije dst,src compare, increment and jump on equal cpijne dst,src compare, increment and jump on non-equal djnz r,dst decrement register and jump on non-zero enter enter exit exit iret interrupt return jp cc,dst jump on condition code jp dst jump unconditional jr cc,dst jump relative on condition code next next ret return wfi wait for interrupt bit manipulation instructions band dst,src bit and bcp dst,src bit compare bitc dst bit complement bitr dst bit reset bits dst bit set bor dst,src bit or bxor dst,src bit xor tcm dst,src test complement under mask tm dst,src test under mask
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 5 table 6-1. instruction group summary ( concluded ) mnemonic operands instruction rotate and shift instructions rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic swap dst swap nibbles cpu control instructions ccf complement carry flag di disable interrupts ei enable interrupts idle enter idle mode nop no operation rcf reset carry flag sb0 set bank 0 sb1 set bank 1 scf set carry flag srp src set register pointers srp0 src set register pointer 0 srp1 src set register pointer 1 stop enter stop mode
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 6 flags register (flags) the flags register flags contains eight bits that describe the current status of cpu operations. four of these bits, f lags.7 ?flags.4, can be tested and used with conditional jump instructions; two others flags.3 and flags.2 are used for bcd arithmetic. the flags register also contains a bit to indicate the status of fast interrupt processing (flags.1) and a bank address status bit (flags.0) to indicate whether bank 0 or bank 1 is currently being addressed. flags register can be set or reset by instructions as long as its outcome does not affect the flags, such as, load instruction. logical and arithmetic instructions such as, and, or, xor, add, and sub can affect the flags register. for example, the and instruction updates the zero, sign and overflow flags based on the outcome of the and instruction. if the and instruction uses the flags register as the destination, then simultaneously, two write will occur to the flags register producing an unpredictable result. system flags register (flags) d5h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb bank address status flag (ba) fast interrupt status flag (fis) half-carry flag (h) decimal adjust flag (d) overflow flag (v) sign flag (s) zero flag (z) carry flag (c) figure 6-1. system flags register (flags)
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 7 flag descriptions c carry flag (flags.7) the c flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (msb). after rotate and shift operations, it contains the last value shifted out of the specified register. program instructions can set, clear, or complement the carry flag. z zero flag (flags.6) for arithmetic and logic operations, the z flag is set to "1" if the result of the operation is zero. for operations that test register bits, and for shift and rotate operations, the z flag is set to "1" if the result is logic zero. s sign flag (flags.5) following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the msb of the result. a logic zero indicates a positive number and a logic one indicates a negative number. v overflow flag (flags.4) the v flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than ? 128. it is also cleared to "0" following logic operations. d decimal adjust flag (flags.3) the da bit is used to specify what type of instruction was executed last during bcd operations, so that a subsequent decimal adjust operation can execute correctly. the da bit is not usually accessed by programmers, and cannot be used as a test condition. h half-carry flag (flags.2) the h bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. it is used by the decimal adjust (da) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (bcd) result. the h flag is seldom accessed directly by a program. fis fast interrupt status flag (flags.1) the fis bit is set during a fast interrupt cycle and reset during the iret following interrupt servicing. when set, it inhibits all interrupts and causes the fast interrupt return to be executed when the iret instruction is executed. ba bank address flag (flags.0) the ba flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. the ba flag is cleared to "0" (select bank 0) when you execute the sb0 instruction and is set to "1" (select bank 1) when you execute the sb1 instruction.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 8 instruction set notation table 6-2. flag notation conventions flag description c carry flag z zero flag s sign flag v overflow flag d decimal-adjust flag h half-carry flag 0 cleared to logic zero 1 set to logic one * set or cleared according to operation ? value is unaffected x value is undefined table 6-3. instruction set symbols symbol description dst destination operand src source operand @ indirect register address prefix pc program counter ip instruction pointer flags flags register (d5h) rp register pointer # immediate operand or register address prefix h hexadecimal number suffix d decimal number suffix b binary number suffix opc opcode
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 9 table 6-4. instruction notation conventions notation description actual operand range cc condition code see list of condition codes in table 6-6. r working register only rn (n = 0?15) rb bit (b) of working register rn.b (n = 0?15, b = 0?7) r0 bit 0 (lsb) of working register rn (n = 0?15) rr working register pair rrp (p = 0, 2, 4, ..., 14) r register or working register reg or rn (reg = 0?255, n = 0?15) rb bit 'b' of register or working register reg.b (reg = 0?255, b = 0?7) rr register pair or working register pair reg or rrp (reg = 0?254, even number only, where p = 0, 2, ..., 14) ia indirect addressing mode addr (addr = 0?254, even number only) ir indirect working register only @rn (n = 0?15) ir indirect register or indirect working register @rn or @reg (reg = 0?255, n = 0?15) irr indirect working register pair only @rrp (p = 0, 2, ..., 14) irr indirect register pair or indirect working register pair @rrp or @reg (reg = 0?254, even only, where p = 0, 2, ..., 14) x indexed addressing mode #reg [rn] (reg = 0?255, n = 0?15) xs indexed (short offset) addressing mode #addr [rrp] (addr = range ?128 to +127, where p = 0, 2, ..., 14) xl indexed (long offset) addressing mode #addr [rrp] (addr = range 0?65535, where p = 0, 2, ..., 14) da direct addressing mode addr (addr = range 0?65535) ra relative addressing mode addr (addr = number in the range +127 to ?128 that is an offset relative to the address of the next instruction) im immediate addressing mode #data (data = 0?255) iml immediate (long) addressing mode #data (data = range 0?65535)
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 10 table 6-5. opcode quick reference opcode map lower nibble (hex) ? 0 1 2 3 4 5 6 7 u 0 dec r1 dec ir1 add r1,r2 add r1,ir2 add r2,r1 add ir2,r1 add r1,im bor r0?rb p 1 rlc r1 rlc ir1 adc r1,r2 adc r1,ir2 adc r2,r1 adc ir2,r1 adc r1,im bcp r1.b, r2 p 2 inc r1 inc ir1 sub r1,r2 sub r1,ir2 sub r2,r1 sub ir2,r1 sub r1,im bxor r0?rb e 3 jp irr1 srp/0/1 im sbc r1,r2 sbc r1,ir2 sbc r2,r1 sbc ir2,r1 sbc r1,im btjr r2.b, ra r 4 da r1 da ir1 or r1,r2 or r1,ir2 or r2,r1 or ir2,r1 or r1,im ldb r0?rb 5 pop r1 pop ir1 and r1,r2 and r1,ir2 and r2,r1 and ir2,r1 and r1,im bitc r1.b n 6 com r1 com ir1 tcm r1,r2 tcm r1,ir2 tcm r2,r1 tcm ir2,r1 tcm r1,im band r0?rb i 7 push r2 push ir2 tm r1,r2 tm r1,ir2 tm r2,r1 tm ir2,r1 tm r1,im bit r1.b b 8 decw rr1 decw ir1 pushud ir1,r2 pushui ir1,r2 mult r2,rr1 mult ir2,rr1 mult im,rr1 ld r1, x, r2 b 9 rl r1 rl ir1 popud ir2,r1 popui ir2,r1 div r2,rr1 div ir2,rr1 div im,rr1 ld r2, x, r1 l a incw rr1 incw ir1 cp r1,r2 cp r1,ir2 cp r2,r1 cp ir2,r1 cp r1,im ldc r1, irr2, xl e b clr r1 clr ir1 xor r1,r2 xor r1,ir2 xor r2,r1 xor ir2,r1 xor r1,im ldc r2, irr2, xl c rrc r1 rrc ir1 cpije ir,r2,ra ldc r1,irr2 ldw rr2,rr1 ldw ir2,rr1 ldw rr1,iml ld r1, ir2 h d sra r1 sra ir1 cpijne irr,r2,ra ldc r2,irr1 call ia1 ld ir1,im ld ir1, r2 e e rr r1 rr ir1 ldcd r1,irr2 ldci r1,irr2 ld r2,r1 ld r2,ir1 ld r1,im ldc r1, irr2, xs x f swap r1 swap ir1 ldcpd r2,irr1 ldcpi r2,irr1 call irr1 ld ir2,r1 call da1 ldc r2, irr1, xs
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 11 table 6-5. opcode quick reference (cont inued ) opcode map lower nibble (hex) ? 8 9 a b c d e f u 0 ld r1,r2 ld r2,r1 djnz r1,ra jr cc,ra ld r1,im jp cc,da inc r1 next p 1 enter p 2 exit e 3 wfi r 4 sb0 5 sb1 n 6 idle i 7 stop b 8 di b 9 ei l a ret e b iret c rcf h d scf e e ccf x f ld r1,r2 ld r2,r1 djnz r1,ra jr cc,ra ld r1,im jp cc,da inc r1 nop
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 12 condition codes the opcode of a conditional jump always contains a 4-bit field called the condition code (cc). this specifies under which conditions it is to execute the jump. for example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. condition codes are listed in table 6-6. the carry (c), zero (z), sign (s), and overflow (v) flags are used to control the operation of conditional jump instructions. table 6-6. condition codes binary mnemonic description flags set 0000 f always false ? 1000 t always true ? 0111 (note) c carry c = 1 1111 (note) nc no carry c = 0 0110 (note) z zero z = 1 1110 (note) nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 (note) eq equal z = 1 1110 (note) ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0 0001 lt less than (s xor v) = 1 1010 gt greater than (z or (s xor v)) = 0 0010 le less than or equal (z or (s xor v)) = 1 1111 (note) uge unsigned greater than or equal c = 0 0111 (note) ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 notes: 1. it indicate s condition codes that are related to two different mnemonics but which test the same flag. for exampl e, z and eq are both true if the zero flag (z) is set, but after an add instruction, z would probably be used; after a cp instruction, however, eq would probably be used. 2. for operations involving unsigned numbers, the special condition codes uge, ult, ugt, and ule must be used.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 13 instruction descriptions this section contains detailed information and programming examples for each instruction in the sam8rc instruction set. information is arranged in a consistent format for improved readability and for fast referencing. the following information is included in each instruction description: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? shorthand notation of the instruction's operation ? textual description of the instruction's effect ? specific flag settings affected by the instruction ? detailed description of the instruction's format, execution time, and addressing mode(s) ? programming example(s) explai ning how to use the instruction
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 14 adc ? add with carry adc dst,src operation: dst ? dst + src + c the source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's- complement addition is performed. in multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 r r 6 15 r ir opc dst src 3 6 16 r im example: given: r1 = 10h, r2 = 03h, c flag = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: adc r1,r2 ? r1 = 14h, r2 = 03h adc r1,@r2 ? r1 = 1bh, r2 = 03h adc 01h,02h ? register 01h = 24h, register 02h = 03h adc 01h,@02h ? register 01h = 2bh, register 02h = 03h adc 01h,#11h ? register 01h = 32h in the first example, destination register r1 contains the value 10h, the carry flag is set to "1", and the source working register r2 contains the value 03h. the statement "adc r1,r2" adds 03h and the carry flag value ("1") to the destination value 10h, leaving 14h in register r1.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 15 add ? add add dst,src operation: dst ? dst + src the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if a carry from the low-order nibble occurred. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 r r 6 05 r ir opc dst src 3 6 06 r im example: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: add r1,r2 ? r1 = 15h, r2 = 03h add r1,@r2 ? r1 = 1ch, r2 = 03h add 01h,02h ? register 01h = 24h, register 02h = 03h add 01h,@02h ? register 01h = 2bh, register 02h = 03h add 01h,#25h ? register 01h = 46h in the first example, destina tion working register r1 contains 12h and the source working register r2 contains 03h. the statement "add r1,r2" adds 03h to 12h, leaving the value 15h in register r1.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 16 and ? logical and and dst,src operation: dst ? dst and src the source operand is logically anded with the destination operand. the result is stored in the destination. the and operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. the contents of the source are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 r r 6 55 r ir opc dst src 3 6 56 r im example: given: r1 = 12h, r2 = 03h, register 01h = 21h , register 02h = 03h, register 03h = 0ah: and r1,r2 ? r1 = 02h, r2 = 03h and r1,@r2 ? r1 = 02h, r2 = 03h and 01h,02h ? register 01h = 01h, register 02h = 03h and 01h,@02h ? register 01h = 00h, register 02h = 03h and 01h,#25h ? register 01h = 21h in the first example, destination working register r1 contains the value 12h and the source working register r2 contains 03h. the statement "and r1,r2" logically ands the source operand 03h with the destination operand value 12h, leaving the value 02h in register r1.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 17 band ? bit and band dst,src.b band dst.b,src operation: dst(0) ? dst(0) and src(b) or dst(b) ? dst(b) and src(0) the specified bit of the source (or the destination) is logically anded with the zero bit (lsb) of the destination (or source). the resultant bit is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 67 r0 rb opc src | b | 1 dst 3 6 67 rb r0 note : in the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h and register 01h = 05h: band r1,01h.1 ? r1 = 06h, register 01h = 05h band 01h.1,r1 ? register 01h = 05h, r1 = 07h in the first example, source register 01h contains the value 05h (00000101b) and destination working register r1 contains 07h (00000111b). the statement "band r1,01h.1" ands the bit 1 value of the source register ("0") with the bit 0 value of register r1 (destination), leaving the value 06h (00000110b) in register r1.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 18 bcp ? bit compare bcp dst,src.b operation: dst(0) ? src(b) the specified bit of the source is compared to (subtracted from) bit zero (lsb) of the destination. the zero flag is set if the bits are the same; otherwise it is cleared. the contents of both operands are unaffected by the comparison. flags: c: unaffected. z: set if the two bits are the same; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 17 r0 rb note : in the second byte of the instruction format, the destination address is four bits, t he bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h and register 01h = 01h: bcp r1,01h.1 ? r1 = 07h, register 01h = 01h if destination working register r1 contains the value 07h (00000111b) and the source register 01h contains the value 01h (00000001b), the statement "bcp r1,01h.1" compares bit one of the source register (01h) and bit zero of the destination register (r1). because the bit values are not identical, the zero flag bit (z) is cleared in the flags register (0d5h).
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 19 bitc ? bit complement bitc dst.b operation: dst(b) ? not dst(b) this instruction complements the specified bit within the destination without affecting any other bits in the destination. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 0 2 4 57 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h bitc r1.1 ? r1 = 05h if working register r1 contains the value 07h (00000111b), the statement "bitc r1.1" complements bit one of the destination and leaves the value 05h (00000101b) in register r1. because the result of the complement is not "0", the zero flag (z) in the flags register (0d5h) is cleared.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 20 bitr ? bit reset bitr dst.b operation: dst(b) ? 0 the bitr instruction clears the specified bit within the destination without affecting any other bits in the destination. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 0 2 4 77 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: bitr r1.1 ? r1 = 05h if the value of worki ng register r1 is 07h (00000111b), the statement "bitr r1.1" clears bit one of the destination register r1, leaving the value 05h (00000101b).
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 21 bits ? bit set bits dst.b operation: dst(b) ? 1 the bits instruction sets the specified bit within the destination without affecting any other bits in the destination. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 1 2 4 77 rb note : in the second byte of the instruction format, the desti nation address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: bits r1.3 ? r1 = 0fh if working register r1 contains the value 07h (00000111b), the statement "bits r1.3" sets bit three of the destination register r1 to "1", leaving the value 0fh (00001111b).
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 22 bor ? bit or bor dst,src.b bor dst.b,src operation: dst(0) ? dst(0) or src(b) or dst(b) ? dst(b) or src(0) the specified bit of the source (o r the destination) is logically ored with bit zero (lsb) of the destination (or the source). the resulting bit value is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 07 r0 rb opc src | b | 1 dst 3 6 07 rb r0 note : in the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit. example: given: r1 = 07h and register 01h = 03h: bor r1, 01h.1 ? r1 = 07h, register 01h = 03h bor 01h.2, r1 ? register 01h = 07h, r1 = 07h in the first example, destination working register r1 contains the value 07h (00000111b) and source register 01h the value 03h (00000011b). the statement "bor r1,01h.1" logically ors bit one of register 01h (source) with bit zero of r1 (destination). this leaves the same value (07h) in working register r1. in the second example, destination register 01h contains the value 03h (00000011b) and the source working register r1 the value 07h (00000111b). the statement "bor 01h.2,r1" logically ors bit two of register 01h (destination) with bit zero of r1 (source). this leaves the value 07h in register 01h.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 23 btjrf ? bit test, jump relative on false btjrf dst,src.b operation: if src(b) is a "0", then pc ? pc + dst the specified bit within the source operand is tested. if it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the pc; otherwise, the instruction following the btjrf instruction is executed. flags: no flags are affected. format: (note 1) bytes cycles opcode (hex) addr mode dst src opc src | b | 0 dst 3 1 0 37 ra rb note: in the second byte of the instructi on format, the source address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: btjrf skip,r1.3 ? pc jumps to skip location if working register r1 contains the value 07h (00000111b), the statement "btjrf skip,r1.3" tests bit 3. because it is "0", the relative address is added to the pc and the pc jumps to the memory location pointed to by the skip. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 24 btjrt ? bit test, jump relative on true btjrt dst,src.b operation: if src(b) is a "1", then pc ? pc + dst the specified bit within the source operand is tested. if it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the pc; otherwise, the instruction following the btjrt instruction is executed. flags: no flags are affected. format: (note 1) bytes cycles opcode (hex) addr mode dst src opc src | b | 1 dst 3 10 37 ra rb note: in the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: btjrt skip,r1.1 if working register r1 contains the value 07h (00000111b), the statement "btjrt skip,r1.1" tests bit one in the source register (r1). because it is a "1", the relative address is added to the pc and the pc jumps to the memory location pointed to by the skip. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 25 bxor ? bit xor bxor dst,src.b bxor dst.b,src operation: dst(0) ? dst(0) xor src(b) or dst(b) ? dst(b) xor src(0) the specified bit of the source (or the destination) is logically exclusive-ored with bit zero (lsb) of the destination (or source). the result bit is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 27 r0 rb opc src | b | 1 dst 3 6 27 rb r0 note : in the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h (00 000111b) and register 01h = 03h (00000011b): bxor r1,01h.1 ? r1 = 06h, register 01h = 03h bxor 01h.2,r1 ? register 01h = 07h, r1 = 07h in the first example, destination working register r1 has the value 07h (00000111b) and source register 01h has the value 03h (00000011b). the statement "bxor r1,01h.1" exclusive-ors bit one of register 01h (source) with bit zero of r1 (destination). the result bit value is stored in bit zero of r1, changing its value from 07h to 06h. the value of source register 01h is unaffected.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 26 call ? call procedure call dst operation: sp ? sp ? 1 @sp ? pcl sp ? sp ?1 @sp ? pch pc ? dst the current contents of the program counter are pushed onto the top of the stack. the program counter value used is the address of the first instruction following the call instruction. the specified destination address is then loaded into the program counter and points to the first instruction of a procedure. at the end of the procedure the return instruction (ret) can be used to return to the original program flow. ret pops the top of the stack back into the program counter. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 3 14 f6 da opc dst 2 12 f4 irr opc dst 2 14 d4 ia example: given: r0 = 35h, r1 = 21h, pc = 1a47h, and sp = 0002h: call 3521h ? sp = 0000h (memory locations 0000h = 1ah, 0001h = 4ah, where 4ah is the address that follows the instruction.) call @rr0 ? sp = 0000h (0000h = 1ah, 0001h = 49h) call #40h ? sp = 0000h (0000h = 1ah, 0001h = 49h) in the first example, if the program counter value is 1a47h and the stack pointer contains the value 0002h, the statement "call 3521h" pushes the current pc value onto the top of the stack. the stack pointer now points to memory location 0000h. the pc is then loaded with the value 3521h, the address of the first instruction in the program sequence to be executed. if the contents of the program counter and stack pointer are the same as in the first example, the statement "call @rr0" produces the same result except that the 49h is stored in stack location 0001h (because the two-byte instruction format was used). the pc is then loaded with the value 3521h, the address of the first instruction in the program sequence to be executed. assuming that the contents of the program counter and stack pointer are the same as in the first example, if program address 0040h contains 35h and program address 0041h contains 21h, the statement "call #40h" produces the same result as in the second example.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 27 ccf ? complement carry flag ccf operation: c ? not c the carry flag (c) is complemented. if c = "1", the value of the carry flag is changed to logic zero; if c = "0", the value of the carry flag is changed to logic one. flags: c: complemented. no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 ef example: given: the carry flag = "0": ccf if the carry flag = "0", the ccf in struction complements it in the flags register (0d5h), changing its value from logic zero to logic one.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 28 clr ? clear clr dst operation: dst ? "0" the destination location is cleared to "0". flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 b0 r 4 b1 ir example: given: register 00h = 4fh, register 01h = 02h, and register 02h = 5eh: clr 00h ? register 00h = 00h clr @01h ? register 01h = 02h, register 02h = 00h in re gister (r) addressing mode, the statement "clr 00h" clears the destination register 00h value to 00h. in the second example, the statement "clr @01h" uses indirect register (ir) addressing mode to clear the 02h register value to 00h.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 29 com ? complement com dst operation: dst ? not dst the contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 60 r 4 61 ir example: given: r1 = 07h and register 07h = 0f1h: com r1 ? r1 = 0f8h com @r1 ? r1 = 07h, register 07h = 0eh in the first example, destination working register r1 contains the value 07h (00000111b). the statement "com r1" complements all the bits in r1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0f8h (11111000b). in the second example, indirect register (ir) addressing mode is used to complement the value of destination register 07h (11110001b), leaving the new value 0eh (00001110b).
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 30 cp ? compare cp dst,src operation: dst ? src the source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. the contents of both operands are unaffected by the comparison. flags: c: set if a "borrow" occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 a2 r r 6 a3 r lr opc src dst 3 6 a4 r r 6 a5 r ir opc dst src 3 6 a6 r im examples: 1. given: r1 = 02h and r2 = 03h: cp r1,r2 ? set the c an d s flags destination working register r1 contains the value 02h and source register r2 contains the value 03h. the statement "cp r1,r2" subtracts the r2 value (source/subtrahend) from the r1 value (destination/minuend). because a "borrow" occurs and the difference is negative, c and s are "1". 2. given: r1 = 05h and r2 = 0ah: cp r1,r2 jp uge,skip inc r1 skip ld r3,r1 in this example, destination working register r1 contains the value 05h which is less than the contents of the source working register r2 (0ah). the statement "cp r1,r2" generates c = "1" and the jp instruction does not jump to the skip location. after the statement "ld r3,r1" executes, the value 06h remains in working register r3.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 31 cpije ? compare, increment, and jump on equal cpije dst,src,ra operation: if dst ? src = "0", pc ? pc + ra ir ? ir + 1 the source operand is compared to (subtracted from) the destination operand. if the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. otherwise, the instruction immediately following the cpije instruction is executed. in either case, the source pointer is incremented by one before the next instruction is executed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst ra 3 1 2 c2 r ir note: execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. example: given: r1 = 02h, r2 = 03h , and register 03h = 02h: cpije r1,@r2,skip ? r2 = 04h, pc jumps to skip location in this example, working register r1 contains the value 02h, working register r2 the value 03h, and register 03 contains 02h. the statement "cpije r1,@r2,skip" compares the @r2 value 02h (00000010b) to 02h (00000010b). because the result of the comparison is equal , the relative address is added to the pc and the pc then jumps to the memory location pointed to by skip. the source register (r2) is incremented by one, leaving a value of 04h. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 32 cpijne ? compare, increment, and jump on non-equal cpijne dst,src,ra operation: if dst ? src _ "0", pc ? pc + ra ir ? ir + 1 the source operand is compared to (subtracted from) the destination operand. if the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the cpijne instruction is executed. in either case the source pointer is incremented by one before the next instruction. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst ra 3 1 2 d2 r ir note: execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. example: given: r1 = 02h, r2 = 03h, and register 03h = 04h: cpijne r1,@r2,skip ? r2 = 04h, pc jumps to skip location working register r1 contains the value 02h, working register r2 (the source pointer) the value 03h, and general register 03 the value 04h. the statement "cpijne r1,@r2,skip" subtracts 04h (00000100b) from 02h (00000010b). because the result of the comparison is non-equal , the relative address is added to the pc and the pc then jumps to the memory location pointed to by skip. the source pointer register (r2) is also incremented by one, leaving a value of 04h. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 33 da ? decimal adjust da dst operation: dst ? da dst the destination operand is adjusted to form two 4-bit bcd digits following an addition or subtraction operation. for addition (add, adc) or subtraction (sub, sbc), the following table indicates the operation performed. (the operation is undefined if the destination operand was not the result of a valid addition or subtraction of bcd digits): instruction carry before da bits 4?7 value (hex) h flag before da bits 0?3 value (hex) number added to byte carry after da 0 0?9 0 0?9 00 0 0 0?8 0 a?f 06 0 0 0?9 1 0?3 06 0 add 0 a?f 0 0?9 60 1 adc 0 9?f 0 a?f 66 1 0 a?f 1 0?3 66 1 1 0?2 0 0?9 60 1 1 0?2 0 a?f 66 1 1 0?3 1 0?3 66 1 0 0?9 0 0?9 00 = ? 00 0 sub 0 0?8 1 6?f fa = ? 06 0 sbc 1 7?f 0 0?9 a0 = ? 60 1 1 6?f 1 6?f 9a = ? 66 1 flags: c: set if there was a carry from the most significant bit; cleared otherwise (see table). z: set if result is "0"; cleared otherwise. s: set if result bit 7 is set; cleared otherwise. v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 40 r 4 41 ir
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 34 da ? decimal adjust da (continued) example: given: working register r0 contains the value 15 (bcd), working register r1 contains 27 (bcd), and address 27h contains 46 (bcd): add r1,r0 ; c ? "0", h ? "0", bits 4?7 = 3, bits 0?3 = c, r1 ? 3ch da r1 ; r1 ? 3ch + 06 if addition is performed using the bcd values 15 and 27, the result should be 42. the sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic: 0 0 0 1 0 1 0 1 15 + 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 = 3ch the da instruction adjusts this result so that the correct bcd representation is obtained: 0 0 1 1 1 1 0 0 + 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 = 42 assuming the same values given above, the statements sub 27h,r0 ; c ? "0", h ? "0", bits 4?7 = 3, bits 0?3 = 1 da @r1 ; @r1 ? 31?0 leave the value 31 (bcd) in address 27h (@r1).
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 35 dec ? decrement dec dst operation: dst ? dst ? 1 the contents of the destination operand are decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 00 r 4 01 ir example: given: r1 = 03h and register 03h = 10h: dec r1 ? r1 = 02h dec @r1 ? register 03h = 0fh in the first example, if working register r1 contains the value 03h, the statement "dec r1" decrements the hexadecimal value by one, leaving the value 02h. in the second example, the statement "dec @r1" decrements the value 10h contained in the destination register 03h by one, leaving the value 0fh.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 36 decw ? decrement word decw dst operation: dst ? dst ? 1 the contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 80 rr 8 81 ir example: given: r0 = 12h, r1 = 34h, r2 = 30h, register 30h = 0f h, and register 31h = 21h: decw rr0 ? r0 = 12h, r1 = 33h decw @r2 ? register 30h = 0fh, register 31h = 20h in the first example, destination register r0 contains the value 12h and register r1 the value 34h. the statement "decw rr0" addresses r0 and the following operand r1 as a 16-bit word and decrements the value of r1 by one, leaving the value 33h. note: a system malfunction may occur if you use a zero flag (flags.6) result together with a decw instruction. to avoid this problem, we recommend that you use decw as shown in the following example: loop: decw rr0 ld r2,r1 or r2,r0 jr nz,loop
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 37 di ? disable interrupts di operation: sym (0) ? 0 bit zero of the system mode control register, sym.0, is cleared to "0", globally disabling all interrupt processing. interrupt requests will continue to set their respective interrupt pending bits, but the cpu will not service them while interrupt processing is disabled. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 8f example: given: sym = 01h: di if the value of the sym register is 01h, the statement "di" leaves the new value 00h in the register and clears sym.0 to "0", disabling interrupt processing. before changing imr, interrupt pending and interrupt source control register, be sure di state.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 38 div ? divide (unsigned) div dst,src operation: dst src dst (upper) ? remainder dst (lower) ? quotient the destination operand (16 bits) is divided b y the source operand (8 bits). the quotient (8 bits) is stored in the lower half of the destination. the remainder (8 bits) is stored in the upper half of the destination. when the quotient is 3 2 8 , the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. both operands are treated as unsigned integers. flags: c: set if the v flag is set and quotient is between 2 8 and 2 9 ?1; cleared otherwise. z: set if divisor or quotient = "0"; cleared otherwise. s: set if msb of quotient = "1"; cleared otherwise. v: set if quotient is 3 2 8 or if divisor = "0"; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 2 6 /1 0 94 rr r 2 6 /1 0 95 rr ir 2 6 /1 0 96 rr im note: execution takes 1 0 cycles if the divide-by-zero is attempted; otherwise it takes 2 6 cycles. examples: given: r0 = 10h, r1 = 03h, r2 = 40h, register 40h = 80h: div rr0,r2 ? r0 = 03h, r1 = 40h div rr0,@r2 ? r0 = 03h, r1 = 20h div rr0,#20h ? r0 = 03h, r1 = 80h in the first example, destination working register pair rr0 contains the values 10h (r0) and 03h (r1), and register r2 contains the value 40h. the statement "div rr0,r2" divides the 16-bit rr0 value by the 8-bit value of the r2 (source) register. after the div instruction, r0 contains the value 03h and r1 contains 40h. the 8-bit remainder is stored in the upper half of the destination register rr0 (r0) and the quotient in the lower half (r1).
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 39 djnz ? decrement and jump if non-zero djnz r,dst operation: r ? r ? 1 if r _ 0, pc ? pc + dst the working register being used as a counter is decremented. if the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the pc. the range of the relative address is +127 to ?128, and the original value of the pc is taken to be the address of the instruction byte following the djnz statement. note: in case of using djnz instruction, the working register being used as a counter should be set at the one of location 0c0h to 0cfh with srp, srp0, or srp1 instruction. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst r | opc dst 2 8 (jump taken) ra ra 8 (no jump) r = 0 to f example: given: r1 = 02h and loop is the label of a relative address: srp #0c0h djnz r1, loop djnz is typically used to control a "loop" of instructions. in many cases, a label is used as the destination operand instead of a numeric relative address value. in the example, working register r1 contains the value 02h, and loop is the label for a relative address. the statement "djnz r1, loop" decrements register r1 by one, leaving the value 01h. because the contents of r1 after the decrement are non-zero, the jump is taken to the relative address specified by the loop label.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 40 ei ? enable interrupts ei operation: sym (0) ? 1 an ei instruction sets bit zero of the system mode register, sym.0 to "1". this allows interrupts to be serviced as they occur (assuming they have highest priority). if an interrupt's pending bit was set while interrupt processing was disabled (by executing a di instruction), it will be serviced when you execute the ei instruction. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 9f example: given: sym = 00h: ei if t he sym register contains the value 00h, that is, if interrupts are currently disabled, the statement "ei" sets the sym register to 01h, enabling all interrupts. (sym.0 is the enable bit for global interrupt processing.)
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 41 enter ? enter enter operation: sp ? sp ? 2 @sp ? ip ip ? pc pc ? @ip ip ? ip + 2 this instruction is useful when implementing threaded-code languages. the contents of the instruction pointer are pushed to the stack. the program counter (pc) value is then written to the instruction pointer. the program memory word that is pointed to by the instruction pointer is loaded into the pc, and the instruction pointer is incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 14 1f example: the diagram below shows one example of how to use an enter statement. 0050 ip 0022 sp 22 data address data 0040 pc 40 41 42 43 enter address h address l address h address data 1f 01 10 memory 0043 ip 0020 sp 20 21 22 iph ipl data address data 0110 pc 40 41 42 43 enter address h address l address h address data 1f 01 10 memory 00 50 stack stack 110 routine before after
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 42 exit ? exit exit operation: ip ? @sp sp ? sp + 2 pc ? @ip ip ? ip + 2 this instruction is useful when implementing t hreaded-code languages. the stack value is popped and loaded into the instruction pointer. the program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 14 (internal stack) 2f 16 (internal stack) example: the diagram below shows one example of how to use an exit statement. 0050 ip 0022 sp address data 0040 pc address data memory 0052 ip 0022 sp address data 0060 pc address data memory stack stack before after 22 data 20 21 22 iph ipl data 00 50 50 51 140 pcl old pch exit 60 00 2f 60 main
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 43 idle ? idle operation idle operation: the idle instruction stops the cpu clock while allowing system clock oscillation to continue. idle mode can be released by an interrupt request (irq) or an external reset operation. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 6f ? ? example: the instruction idle nop nop nop stops the cpu clock but not the system clock.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 44 inc ? increment inc dst operation: dst ? dst + 1 the contents of the destination operand are incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst dst | opc 1 4 re r r = 0 to f opc dst 2 4 20 r 4 21 ir example: given: r0 = 1bh, register 00h = 0ch, and register 1bh = 0fh: inc r0 ? r0 = 1ch inc 00h ? register 00h = 0dh inc @r0 ? r0 = 1bh, register 01h = 10h in the first example, if destination working register r0 contains the value 1bh, the statement "inc r0" leaves the value 1ch in that same register. the next example shows the effect an inc instruction has on register 00h, assuming that it contains the value 0ch. in the third example, inc is used in indirect register (ir) addressing mode to increment the value of register 1bh from 0fh to 10h.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 45 incw ? increment word incw dst operation: dst ? dst + 1 the contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 a0 rr 8 a1 ir example: given: r0 = 1ah, r1 = 02h, register 02h = 0fh, and register 03h = 0ffh: incw rr0 ? r0 = 1ah, r1 = 03h incw @r1 ? register 02h = 10h, register 03h = 00h in the first example, the working register pair rr0 contains the value 1ah in register r0 and 02h in register r1. the statement "incw rr0" increments the 16-bit destination by one, leaving the value 03h in register r1. in the second example, the statement "incw @r1" uses indirect register (ir) addressing mode to increment the contents of general register 03h from 0ffh to 00h and register 02h from 0fh to 10h. note: a system malfunction may occur if you use a zero (z) flag (flags.6) result together with an incw instruction. to avoid this problem, we recommend that you use incw as shown in the following example: loop: incw rr0 ld r2,r1 or r2,r0 jr nz,loop
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 46 iret ? interrupt return iret iret (normal) iret (fast) operation: flags ? @sp pc ? ip sp ? sp + 1 flags ? flags' pc ? @sp fis ? 0 sp ? sp + 2 sym(0) ? 1 this instruction is used at the end of an interrupt service routine. it restores the flag register and the program counter. it also re-enables global interrupts. a "normal iret" is executed only if the fast interrupt status bit (fis, bit one of the flags register, 0d5h) is cleared (= "0"). if a fast interrupt occurred, iret clears the fis bit that was set at the beginning of the service routine. flags: all flags are restored to their original settings (that is, the settings before the interrupt occurred). format: iret (normal) bytes cycles opcode (hex) opc 1 1 0 (internal stack) bf 1 2 (external stack) iret (fast) bytes cycles opcode (hex) opc 1 6 bf example: in the figure below, the instruction pointer is initially loaded with 100h in the main program before interrupts are enabled. when an interrupt occurs, the program counter and instruction pointer are swapped. this causes the pc to jump to address 100h and the ip to keep the return address. the last instruction in the service routine normally is a jump to iret at address ffh. this causes the instruction pointer to be loaded with 100h "again" and the program counter to jump back to the main program. now, the next interrupt can occur and the ip is still correct at 100h. iret interrupt service routine jp to ffh 0h ffh 100h ffffh note: i n the fast interrupt example above, if the last instruction is not a jump to iret, you must pay attention to the order of the last two instructions. the iret cannot be immediately proceeded by a clearing of the interrupt status (as with a reset of the ipr register).
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 47 jp ? jump jp cc,dst (conditional) jp dst (unconditional) operation: if cc is true, pc ? dst the conditional jump instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the jp instruction is executed. the unconditional jp simply replaces the contents of the pc with the contents of the specified register pair. control then passes to the statement addressed by the pc. flags: no flags are affected. format : (1) (2) bytes cycles opcode (hex) addr mode dst cc | opc dst 3 8 ccd da cc = 0 to f opc dst 2 8 30 irr notes : 1. the 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. in the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits. example: given: the carry flag (c) = "1", register 00 = 01h, and register 01 = 20h: jp c,label_w ? label_w = 1000h, pc = 1000h jp @00h ? pc = 0120h the first example shows a conditional jp. assuming that the carry flag is set to "1", the statement "jp c,label_w" replaces the contents of the pc with the value 1000h and transfers control to that location. had the carry flag not been set, control would then have passed to the statement immediately following the jp instruction. the second example shows an unconditional jp. the statement "jp @00" replaces the contents of the pc with the contents of the register pair 00h and 01h, leaving the value 0120h.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 48 jr ? jump relative jr cc,dst operation: if cc is true, pc ? pc + dst if the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the jr instruction is executed. (see list of condition codes). the range of the relative address is +127, ?128, and the original value of the program counter is taken to be the address of the first instruction byte following the jr statement. flags: no flags are affected. format: (1) bytes cycles opcode (hex) addr mode dst cc | opc dst 2 6 ccb ra cc = 0 to f note : in the first byte of the two-byte instruction format, the condition code and the opcode are each four bits. example: given: the carry flag = "1" and label_x = 1ff7h: jr c,label_x ? pc = 1ff7h if the carry flag is set (that is, if the condition code is true), the statement "jr c,label_x" will pass control to the statement whose address is now in the pc. otherwise, the program instruction following the jr would be executed.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 49 ld ? load ld dst,src operation: dst ? src the contents of the source are loaded into the destination. the source's contents are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src dst | opc src 2 4 rc r im 4 r8 r r src | opc dst 2 4 r9 r r r = 0 to f opc dst | src 2 4 c7 r lr 4 d7 ir r opc src dst 3 6 e4 r r 6 e5 r ir opc dst src 3 6 e6 r im 6 d6 ir im opc src dst 3 6 f5 ir r opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 50 ld ? load ld (continued) examples: given: r0 = 01h, r1 = 0ah, register 00h = 01h, register 01h = 20h, register 02h = 02h, loop = 30h, and register 3ah = 0ffh: ld r0,#10h ? r0 = 10h ld r0,01h ? r0 = 20h, register 01h = 20h ld 01h,r0 ? register 01h = 01h, r0 = 01h ld r1,@r0 ? r1 = 20h, r0 = 01h ld @r0,r1 ? r0 = 01h, r1 = 0ah, register 01h = 0ah ld 00h,01h ? register 00h = 20h, register 01h = 20h ld 02h,@00h ? register 02h = 20h, register 00h = 01h ld 00h,#0ah ? register 00h = 0ah ld @00h,#10h ? regis ter 00h = 01h, register 01h = 10h ld @00h,02h ? register 00h = 01h, register 01h = 02, register 02h = 02h ld r0,#loop[r1] ? r0 = 0ffh, r1 = 0ah ld #loop[r0],r1 ? register 31h = 0ah, r0 = 01h, r1 = 0ah
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 51 ldb ? load bit ldb dst,src.b ldb dst.b,src operation: dst(0) ? src(b) or dst(b) ? src(0) the specified bit of the source is loaded into bit zero (lsb) of the destination, or bit zero of the source is loaded into the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 47 r0 rb opc src | b | 1 dst 3 6 47 rb r0 note : in the second byte of the instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. examples: given: r0 = 06h and general register 00h = 05h: ldb r0,00h.2 ? r0 = 0 7h, register 00h = 05h ldb 00h.0,r0 ? r0 = 06h, register 00h = 04h in the first example, destination working register r0 contains the value 06h and the source general register 00h the value 05h. the statement "ld r0,00h.2" loads the bit two value of the 00h register into bit zero of the r0 register, leaving the value 07h in register r0. in the second example, 00h is the destination register. the statement "ld 00h.0,r0" loads bit zero of register r0 to the specified bit (bit zero) of the destination register, leaving 04h in general register 00h.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 52 ldc/lde ? load memory ldc/lde dst,src operation: dst ? src this instruction loads a byte from program or data memory into a working register or vice-versa. the source values are unaffected. ldc refers to program memory and lde to data memory. the assembler makes 'irr' or 'rr' values an even number for program memory and odd an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src 1. opc dst | src 2 1 0 c3 r irr 2. opc src | dst 2 1 0 d3 irr r 3. opc dst | src xs 3 1 2 e7 r xs [rr] 4. opc src | dst xs 3 1 2 f7 xs [rr] r 5. opc dst | src xl l xl h 4 14 a7 r xl [rr] 6. opc src | dst xl l xl h 4 14 b7 xl [rr] r 7. opc dst | 0000 da l da h 4 14 a7 r da 8. opc src | 0000 da l da h 4 14 b7 da r 9. opc dst | 0001 da l da h 4 14 a7 r da 10. opc src | 0001 da l da h 4 14 b7 da r notes : 1. the source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0 ?1. 2. for formats 3 and 4, the destination address 'xs [rr]' and the source address 'xs [rr]' are each one byte. 3. for formats 5 and 6, the destination address 'xl [rr] and the source address 'xl [rr]' are each two bytes. 4. the da and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 53 ldc/lde ? load memory ldc/lde (continued) examples: given: r0 = 11h, r1 = 34h, r2 = 01h, r3 = 04h; program memory locations 0103h = 4fh, 0104h = 1a, 0105h = 6dh, and 1104h = 88h. external data memory locations 0103h = 5fh, 0104h = 2ah, 0105h = 7dh, and 1104h = 98h: ldc r0,@rr2 ; r0 ? contents of program memory location 0104h ; r0 = 1ah, r2 = 01h, r3 = 04h lde r0,@rr2 ; r0 ? contents of external data memory location 0104h ; r0 = 2ah, r2 = 01h , r3 = 04h ldc (note) @rr2,r0 ; 11h (contents of r0) is loaded into program memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change lde @rr2,r0 ; 11h (contents of r0) is loaded into external data memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change ldc r0,#01h[rr2] ; r0 ? contents of program memory location 0105h ; (01h + rr2), ; r0 = 6dh, r2 = 01h, r3 = 04h lde r0,#01h[rr2] ; r0 ? contents of external data memory location 0105h ; (01 h + rr2), r0 = 7dh, r2 = 01h, r3 = 04h ldc (note) #01h[rr2],r0 ; 11h (contents of r0) is loaded into program memory location ; 0105h (01h + 0104h) lde #01h[rr2],r0 ; 11h (contents of r0) is loaded into external data memory ; location 0105h (01h + 0104h) ldc r0,#1000h[rr2] ; r0 ? contents of program memory location 1104h ; (1000h + 0104h), r0 = 88h, r2 = 01h, r3 = 04h lde r0,#1000h[rr2] ; r0 ? contents of external data memory location 1104h ; (1000h + 0104h), r0 = 98h, r2 = 0 1h, r3 = 04h ldc r0,1104h ; r0 ? contents of program memory location 1104h, r0 = 88h lde r0,1104h ; r0 ? contents of external data memory location 1104h, ; r0 = 98h ldc (note) 1105h,r0 ; 11h (contents of r0) is loaded into program memory location ; 1105h, (1105h) ? 11h lde 1105h,r0 ; 11h (contents of r0) is loaded into external data memory ; location 1105h, (1105h) ? 11h note: these instructions are not supported by masked rom type devices.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 54 ldcd/lded ? load memory and decrement ldcd/lded dst,src operation: dst ? src rr ? rr ? 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then decremented. the contents of the source are unaffected. ldcd references program memory and lded references external data memory. th e assembler makes 'irr' an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 1 0 e2 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory location 1033h = 0cdh, and external data memory location 1033h = 0ddh: ldcd r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is decremented by one ; r8 = 0cdh, r6 = 10h , r7 = 32h (rr6 ? rr6 ? 1) lded r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is decremented by one (rr6 ? rr6 ? 1) ; r8 = 0ddh, r6 = 10h, r7 = 32h
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 55 ldci/ldei ? load memory and increment ldci/ldei dst,src operation: dst ? src rr ? rr + 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then incremented automatically. the contents of the source are unaffected. ldci refers to program memory and ldei refers to external data memory. the assembler makes 'irr' even for program memory and odd for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 1 0 e3 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12 h, program memory locations 1033h = 0cdh and 1034h = 0c5h; external data memory locations 1033h = 0ddh and 1034h = 0d5h: ldci r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 ? rr6 + 1) ; r8 = 0cdh, r6 = 10h, r7 = 34h ldei r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 ? rr6 + 1) ; r8 = 0ddh, r6 = 10h, r7 = 34h
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 56 ldcpd/ldepd ? load memory with pre-decrement ldcpd/ ldepd dst,src operation: rr ? rr ? 1 dst ? src these instructions are used for block transfers of data from program or data memory from the register file. the address of the memory location is specified by a working register pair and is first decremented. the contents of the source location are then loaded into the destination location. the contents of the source are unaffected. ldcpd refers to program memory and ldepd refers to external data memory. the assembler makes 'irr' an even number for program memory and an odd number for external data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src | dst 2 1 4 f2 irr r examples: given: r0 = 77h, r6 = 30h, and r7 = 00h: ldcpd @rr6,r0 ; (rr6 ? rr6 ? 1) ; 77h (contents of r0) is loaded into program memory location ; 2fffh (3000h ? 1h) ; r0 = 77h, r6 = 2fh, r7 = 0ffh ldepd @rr6,r0 ; (rr6 ? rr6 ? 1) ; 77h (contents of r0) is l oaded into external data memory ; location 2fffh (3000h ? 1h) ; r0 = 77h, r6 = 2fh, r7 = 0ffh
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 57 ldcpi/ldepi ? load memory with pre-increment ldcpi/ ldepi dst,src operation: rr ? rr + 1 dst ? src these instructions are used for block transfers of data from program or data memory from the register file. the address of the memory location is specified by a working register pair and is first incremented. the contents of the source location are loaded into the destination location. the contents of the source are unaffected. ldcpi refers to program memory and ldepi refers to external data memory. the assembler makes 'irr' an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src | dst 2 1 4 f3 irr r examples: given: r0 = 7fh, r6 = 21h, and r7 = 0ffh: ldcpi @rr6,r0 ; (rr6 ? rr6 + 1) ; 7fh (contents of r0) is loaded into program memory ; loca tion 2200h (21ffh + 1h) ; r0 = 7fh, r6 = 22h, r7 = 00h ldepi @rr6,r0 ; (rr6 ? rr6 + 1) ; 7fh (contents of r0) is loaded into external data memory ; location 2200h (21ffh + 1h) ; r0 = 7fh, r6 = 22h, r7 = 00h
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 58 ldw ? load word ldw dst,src operation: dst ? src the contents of the source (a word) are loaded into the destination. the contents of the source are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 c4 rr rr 8 c5 rr ir opc dst src 4 8 c6 rr iml examples: given: r4 = 06h, r5 = 1ch, r6 = 05h, r7 = 02h, register 00h = 1ah, register 01h = 02h, register 02h = 03h, and register 03h = 0fh: ldw rr6,rr4 ? r6 = 06h, r7 = 1ch, r4 = 06h, r5 = 1ch ldw 00h,02h ? register 00h = 03h, register 01h = 0fh, register 02h = 03h, register 03h = 0fh ldw rr2,@r7 ? r2 = 03h, r3 = 0fh, ldw 04h,@01h ? register 04h = 03h, register 05h = 0fh ldw rr6 ,#1234h ? r6 = 12h, r7 = 34h ldw 02h,#0fedh ? register 02h = 0fh, register 03h = 0edh in the second example, please note that the statement "ldw 00h,02h" loads the contents of the source word 02h, 03h into the destination word 00h, 01h. this leaves the value 03h in general register 00h and the value 0fh in register 01h. the other examples show how to use the ldw instruction with various addressing modes and formats.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 59 mult ? multiply (unsigned) mult dst,src operation: dst ? dst src the 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. both operands are treated as unsigned integers. flags: c: set if result is > 255; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if msb of the result is a "1"; cleared otherwise. v: cleared. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 2 2 84 rr r 2 2 85 rr ir 2 2 86 rr im examples: given: register 00h = 20h, register 01h = 03h, register 02h = 09h, register 03h = 06h: mult 00h, 02h ? register 00h = 01h, register 01h = 20h, register 02h = 09h mult 00h, @01h ? register 00h = 00h, register 01h = 0c0h mult 00h, #30h ? register 00h = 06h, register 01h = 00h in the first example, the statement "mult 00h,02h" multiplies the 8-bit destination operand (in the register 00h of the register pair 00h, 01h) by the source register 02h operand (09h). the 16 -bit product, 0120h, is stored in the register pair 00h, 01h.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 60 next ? next next operation: pc ? @ ip ip ? ip + 2 the next instruction is useful when implementing threaded-code languages. the program memory word that is pointed to by the instruction pointer is loaded into the program counter. the instruction pointer is then incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 1 0 0f example: the following diagram shows one example of how to use the next instruction. data 01 10 before after 0045 ip address data 0130 pc 43 44 45 address h address l address h address data memory 130 routine 0043 ip address data 0120 pc 43 44 45 address h address l address h address data memory 120 next
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 61 nop ? no operation nop operation: no action is performed when the cpu executes this instruction. typically, one or more nops are executed in sequence in order to effect a timing delay of variable duration. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 ff example: when the instruction nop is encountered in a program, no operation occurs. instead, there is a delay in instruction execution time.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 62 or ? logical or or dst,src operation: dst ? dst or src the source operand is logically ored with the destination operand and the result is stored in the destination. the contents of the source are unaffected. the or operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. flags: c: unaffected. z: set if the resul t is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 r r 6 45 r ir opc dst src 3 6 46 r im examples: given: r0 = 15h, r1 = 2ah, r2 = 01h, register 00h = 08h, register 01h = 37h, and register 08h = 8ah: or r0,r1 ? r0 = 3fh, r1 = 2ah or r0,@r2 ? r0 = 37h, r2 = 01h, register 01h = 37h or 00h,01h ? register 00h = 3fh, register 01h = 37h or 01h,@00h ? register 00h = 08h, register 01h = 0bfh or 00h,#02h ? register 00h = 0ah in the first example, if working register r0 contains the value 15h and register r1 the value 2ah, the statement "or r0,r1" logical-ors the r0 and r1 register contents and stores the result (3fh) in destination register r0. the other examples show the use of the logical or instruction with the various addressing modes and formats.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 63 pop ? pop from stack pop dst operation: dst ? @sp sp ? sp + 1 the contents of the location addressed by the stack pointer are loaded into the destination. the stack pointer is then incremented by one. flags: no flags affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 50 r 8 51 ir examples: given: register 00h = 01h, register 01h = 1bh, sph (0d8h) = 00h, spl (0d9h) = 0fbh, and stack register 0fbh = 55h: pop 00h ? register 00h = 55h, sp = 00fch pop @00h ? register 00h = 01h, register 01h = 55h, sp = 00fch in the first example, general register 00h contains the value 01h. the statement "pop 00h" loads the contents of location 00fbh (55h) into destination register 00h and then increments the stack pointer by one. register 00h then contains the value 55h and the sp points to location 00fch.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 64 popud ? pop user stack (decrementing) popud dst,src operation: dst ? src ir ? ir ? 1 this instruction is used for user-defined stacks in the register file. the contents of the register file location addressed by the user stack pointer are loaded into the destination. the user stack pointer is then decremented. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 92 r ir example: given: register 00h = 42h (user stack pointer register), register 42h = 6fh, and register 02h = 70h: popud 02h,@00h ? register 00h = 41 h, register 02h = 6fh, register 42h = 6fh if general register 00h contains the value 42h and register 42h the value 6fh, the statement "popud 02h,@00h" loads the contents of register 42h into the destination register 02h. the user stack pointer is then decremented by one, leaving the value 41h.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 65 popui ? pop user stack (incrementing) popui dst,src operation: dst ? src ir ? ir + 1 the popui instruction is used for user-defined stacks in the register file. the contents of the register file location addressed by the user stack pointer are loaded into the destination. the user stack pointer is then incremented. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 93 r ir example: given: register 00h = 01h and register 01h = 70h: popui 02h,@00h ? register 00h = 02h, register 01h = 70h, register 02h = 70h if general register 00h contains the value 01h and register 01h the value 70h, the statement "popui 02h,@00h" loads the value 70h into the destination general register 02h. the user stack pointer (register 00h) is then incremented by one, changing its value from 01h to 02h.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 66 push ? push to stack push src operation: sp ? sp ? 1 @sp ? src a push instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. the operation then adds the new value to the top of the stack. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc src 2 8 (internal clock) 70 r 8 (external clock) 8 (internal clock) 8 (external clock) 71 ir examples: given: register 40h = 4fh, register 4fh = 0aah, sph = 00h, and spl = 00h: push 40h ? register 40h = 4fh, stack register 0ffh = 4fh, sph = 0ffh, spl = 0ffh push @40h ? register 40h = 4fh, register 4fh = 0aah, stack register 0ffh = 0aah, sph = 0ffh, spl = 0ffh in the firs t example, if the stack pointer contains the value 0000h, and general register 40h the value 4fh, the statement "push 40h" decrements the stack pointer from 0000 to 0ffffh. it then loads the contents of register 40h into location 0ffffh and adds this new value to the top of the stack.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 67 pushud ? push user stack (decrementing) pushud dst,src operation: ir ? ir ? 1 dst ? src this instruction is used to address user-defined stacks in the register file. pushud decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst src 3 8 82 ir r example: given: register 00h = 03h, register 01h = 05h, and register 02h = 1ah: pushud @00h,01h ? register 00h = 02h, register 01h = 05h, register 02h = 05h if the user stack pointer (register 00h, for example) contains the value 03h, the statement "pushud @00h,01h" decrements the user stack pointer by one, leaving the value 02h. the 01h register value, 05h, is then loaded into the register addressed by the decremented user stack pointer.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 68 pushui ? push user stack (incrementing) pushui dst,src operation: ir ? ir + 1 dst ? src this instruction is used for user-defined stacks in the register file. pushui increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst src 3 8 83 ir r example: given: register 00h = 03h, register 01h = 05h, and register 04h = 2ah: pushui @00h,01h ? register 00h = 04h, register 01h = 05h, register 04h = 05h if the user stack pointer (register 00h, for example) contains the value 03h, the statement "pushui @00h,01h" increments the user stack pointer by one, leaving the value 04h. the 01h register value, 05h, is then loaded into the location addressed by the incremented user stack pointer.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 69 rcf ? reset carry flag rcf rcf operation: c ? 0 the carry flag is cleared to logic zero, regardless of its previous value. flags: c: cleared to "0". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 cf example: given: c = "1" or "0": the instruction rcf clears the carry flag (c) to logic zero.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 70 ret ? return ret operation: pc ? @sp sp ? sp + 2 the ret instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a call instruction. the contents of the location addressed by the stack pointer are popped into the program counter. the next statement that is executed is the one that is addressed by the new program counter value. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 8 (internal stack) af 10 (external stack) example: given: sp = 00fch, (sp) = 101ah, and pc = 1234: ret ? pc = 101ah, sp = 00feh the statement "ret" pops the contents of stack pointer location 00fch (10h) into the high byte of the program counter. the stack pointer then pops the value in location 00feh (1ah) into the pc's low byte and the instruction at location 101ah is executed. the stack pointer now points to memory location 00feh.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 71 rl ? rotate left rl dst operation: c ? dst (7) dst (0) ? dst (7) dst (n + 1) ? dst (n), n = 0?6 the contents of the destination operand are rotated left one bit position. the initial value of bit 7 is moved to the bit zero (lsb) position and also replaces the carry flag. 7 0 c flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 90 r 4 91 ir examples: given: register 00h = 0aah, register 01h = 02h and register 02h = 17h: rl 00h ? register 00h = 55h, c = "1" rl @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h contains the value 0aah (10101010b), the statement "rl 00h" rotates the 0aah value left one bit position, leaving the new value 55h (01010101b) and setting the carry and overflow flags.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 72 rlc ? rotate left through carry rlc dst operation: dst (0) ? c c ? dst (7) dst (n + 1) ? dst (n), n = 0?6 the contents of the destination operand with the carry flag are rotated left one bit position. the initial value of bit 7 replaces the carry flag (c); the initial value of the carry flag replaces bit zero. 7 0 c flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 10 r 4 11 ir examples: given: register 00h = 0aah, register 01h = 02h, and register 02h = 17h, c = "0": rlc 00h ? register 00h = 54h, c = "1" rlc @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if ge neral register 00h has the value 0aah (10101010b), the statement "rlc 00h" rotates 0aah one bit position to the left. the initial value of bit 7 sets the carry flag and the initial value of the c flag replaces bit zero of register 00h, leaving the value 55h (01010101b). the msb of register 00h resets the carry flag to "1" and sets the overflow flag.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 73 rr ? rotate right rr dst operation: c ? dst (0) dst (7) ? dst (0) dst (n) ? dst (n + 1), n = 0?6 the contents of the destination operand are rotated right one bit position. the initial value of bit zero (lsb) is moved to bit 7 (msb) and also replaces the carry flag (c). 7 0 c flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 e0 r 4 e1 ir examples: given: register 00h = 31h, register 01h = 02h, and register 02h = 17h: rr 00h ? register 00h = 98h, c = "1" rr @01h ? register 01h = 02h, register 02h = 8bh, c = "1" in the first example, if general register 00h contains the value 31h (00110001b), the statement "rr 00h" rotates this value one bit position to the right. the initial value of bit zero is moved to bit 7, leaving the new value 98h (10011000b) in the destination register. the initial bit zero also resets the c flag to "1" and the sign flag and overflow flag are also set to "1".
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 74 rrc ? rotate right through carry rrc dst operation: dst (7) ? c c ? dst (0) dst (n) ? dst (n + 1), n = 0?6 the contents of the destination operand and the carry flag are rotated right one bit position. the initial value of bit zero (lsb) replaces the carry flag; the initial value of the carry flag replaces bit 7 (msb). 7 0 c flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0" cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 c0 r 4 c1 ir examples: given: register 00 h = 55h, register 01h = 02h, register 02h = 17h, and c = "0": rrc 00h ? register 00h = 2ah, c = "1" rrc @01h ? register 01h = 02h, register 02h = 0bh, c = "1" in the first example, if general register 00h contains the value 55h (01010101b), the statement "rrc 00h" rotates this value one bit position to the right. the initial value of bit zero ("1") replaces the carry flag and the initial value of the c flag ("1") replaces bit 7. this leaves the new value 2ah (00101010b) in destination register 00h. the sign flag and overflow flag are both cleared to "0".
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 75 sb0 ? select bank 0 sb0 operation: bank ? 0 the sb0 instruction clears the bank address flag in the flags register (flags.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 4f example: the statement sb0 clears flags.0 to "0", selecting bank 0 register addressing.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 76 sb1 ? select bank 1 sb1 operation: bank ? 1 the sb1 instruction sets the bank address flag in the flags register (flags.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (bank 1 is not implemented in some ks88-series microcontrollers.) flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 5f example: the statement sb1 sets flags.0 to "1", selecting bank 1 register addressing, if implemented.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 77 sbc ? subtract with carry sbc dst,src operation: dst ? dst ? src ? c the source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's-complement of the source operand to the destination operand. in multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. flags: c: set if a borrow occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 r r 6 35 r ir opc dst src 3 6 36 r im examples: given: r1 = 10h, r2 = 03h, c = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: sbc r1,r2 ? r1 = 0ch, r2 = 03h sbc r1,@r2 ? r1 = 05h, r2 = 03h, register 03h = 0ah sbc 01h,02h ? register 01h = 1ch, register 02h = 03h sbc 01h,@02h ? register 01h = 15h,register 02h = 03h, register 03h = 0ah sbc 01h,#8ah ? register 01h = 95h; c, s, and v = "1" in the first example, if working register r1 contains the value 10h and register r2 the value 03h, the statement "sbc r1,r2" subtracts the source value (03h) and the c flag value ("1") from the destination (10h) and then stores the result (0ch) in register r1.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 78 scf ? set carry flag scf operation: c ? 1 the carry flag (c) is set to logic one, rega rdless of its previous value. flags: c: set to "1". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 df example: the statement scf sets the carry flag to logic one.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 79 sra ? shift right arithmetic sra dst operation: dst (7) ? dst (7) c ? dst (0) dst (n) ? dst (n + 1), n = 0?6 an arithmetic shift-right of one bit position is performed on the destination operand. bit zero (the lsb) replaces the carry flag. the value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. 7 0 c 6 flags: c: set if the bit shifted from the lsb position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 d0 r 4 d1 ir examples: given: register 00h = 9ah, register 02h = 03h, register 03h = 0bch, and c = "1": sra 00h ? register 00h = 0cd, c = "0" sra @02h ? register 02h = 03h, register 03h = 0deh, c = "0" in the first example, if general register 00h contains the value 9ah (10011010b), the statement "sra 00h" shifts the bit values in register 00h right one bit position. bit zero ("0") clears the c flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). this leaves the value 0cdh (11001101b) in destination register 00h.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 80 srp/srp0/srp1 ? set register pointer srp src srp0 src srp1 src operation: if src (1) = 1 and src (0) = 0 then: rp0 (3 ?7) ? src (3?7) if src (1) = 0 and src (0) = 1 then: rp1 (3 ?7) ? src (3?7) if src (1) = 0 and src (0) = 0 then: rp0 (4 ?7) ? src (4?7), rp0 (3) ? 0 rp1 (4 ?7) ? src (4?7), rp1 (3) ? 1 the source data bits one and zero (lsb) determine whether to write one or both of the register pointers, rp0 and rp1. bits 3?7 of the selected register pointer are written unless both register pointers are selected. rp0.3 is then cleared to logic zero and rp1.3 is set to logic one. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode src opc src 2 4 31 im examples: the statement srp #40h sets register pointer 0 (rp0) at location 0d6h to 40h and register pointer 1 (rp1) at location 0d7h to 48h. the statement "srp0 #50h" sets rp0 to 50h, and the statement "srp1 #68h" sets rp1 to 68h.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 81 stop ? stop operation stop operation: the stop instruction stops the both the cpu c lock and system clock and causes the microcontroller to enter stop mode. during stop mode, the contents of on-chip cpu registers, peripheral registers, and i/o port control and data registers are retained. stop mode can be released by an external reset operation or by external interrupts. for the reset operation, the reset pin must be held to low level until the required oscillation stabilization interval has elapsed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 7f ? ? example: the statement stop nop nop nop halts all microcontroller operations.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 82 sub ? subtract sub dst,src operation: dst ? dst ? src the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's complement of the source operand to the destination operand. flags: c: set if a "borrow" occurred; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 r r 6 25 r ir opc dst src 3 6 26 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: sub r1,r2 ? r1 = 0fh, r2 = 03h sub r1,@r2 ? r1 = 08h, r2 = 03h sub 01h,02h ? register 01h = 1eh, register 02h = 03h sub 01h,@02h ? register 01h = 17h, register 02h = 03h sub 01h,#90h ? register 01h = 91h; c, s, and v = "1" sub 01h,#65h ? register 01h = 0bch; c and s = "1", v = "0" in the first example, if working register r1 contains the value 12h and if register r2 contains the value 03h, the statement "sub r1,r2" subtracts the source value (03h) from the destination value (12h) and stores the result (0fh) in destination register r1.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 83 swap ? swap nibbles swap dst operation: dst (0 ? 3) ? dst (4 ? 7) the contents of the lower four bits and upper four bits of the destination operand are swapped. 7 0 4 3 flags: c: undefined. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 f0 r 4 f1 ir examples: given: register 00h = 3eh, register 02h = 03h, and register 03h = 0a4h: swap 00h ? register 00h = 0e3h swap @02h ? register 02h = 03h, register 03h = 4ah in the first example, if general register 00h contains the va lue 3eh (00111110b), the statement "swap 00h" swaps the lower and upper four bits (nibbles) in the 00h register, leaving the value 0e3h (11100011b).
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 84 tcm ? test complement under mask tcm dst,src operation: (not dst) and src this instruction tests selected bits in the destination operand for a logic one value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). the tcm statement complements the destination operand, which is then anded with the source mask. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 r r 6 65 r ir opc dst src 3 6 66 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 12h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tcm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "1" tcm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tcm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "1" tcm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "1" tcm 00h,#34 ? register 00h = 2bh, z = "0" in the first example, if w orking register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tcm r0,r1" tests bit one in the destination register for a "1" value. because the mask value corresponds to the test bit, the z flag is set to logic one and can be tested to determine the result of the tcm operation.
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 85 tm ? test under mask tm dst,src operation: dst and src this instruction tests selected bits in the destination operand for a logic zero value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is anded with the destination operand. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 r r 6 75 r ir opc dst src 3 6 76 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "0" tm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "0" tm 00h,@01h ? register 00h = 2bh, register 01h = 02h, re gister 02h = 23h, z = "0" tm 00h,#54h ? register 00h = 2bh, z = "1" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tm r0,r1" tests bit one in the destination register for a "0" value. because the mask value does not match the test bit, the z flag is cleared to logic zero and can be tested to determine the result of the tm operation.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 86 wfi ? wait for interrupt wfi operation: the cpu is effe ctively halted until an interrupt occurs, except that dma transfers can still take place during this wait state. the wfi status can be released by an internal interrupt, including a fast interrupt . flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 n 3f ( n = 1, 2, 3, ? ) example: the following sample program structure shows the sequence of operations that follow a "wfi" statement: ei wfi (next instruction) main program . . . . . . interrupt occurs interrupt service routine . . . clear interrupt flag iret service routine completed (enable global interrupt) (wait for interrupt)
s3c8639/c863a/p863a/c8647/f8647 instruction set 6- 87 xor ? logical exclusive or xor dst,src operation: dst ? dst xor src the source operand is logically exclusive-ored with the destination operand and the result is stored in the destination. the exclusive-or operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 b2 r r 6 b3 r lr opc src dst 3 6 b4 r r 6 b5 r ir opc dst src 3 6 b6 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: xor r0,r1 ? r0 = 0c5h, r1 = 02h xor r0,@r1 ? r0 = 0e4h, r1 = 02h, register 02h = 23h xor 00h,01h ? register 00h = 29h, register 01h = 02h xor 00h,@01h ? register 00h = 08h, registe r 01h = 02h, register 02h = 23h xor 00h,#54h ? register 00h = 7fh in the first example, if working register r0 contains the value 0c7h and if register r1 contains the value 02h, the statement "xor r0,r1" logically exclusive-ors the r1 value with the r0 value and stores the result (0c5h) in the destination register r0.
instruction set s3c8639/c863a/p863a /c8647/f8647 6- 88 notes
clock circuit reset reset and power-down i/o ports basic timer timer m0 timer m1 timer m2 analog-to-digital converter pulse width modulat ion sync processor ddc and iic-bus interface slave iic-bus interface electrical data mechanical data s3p863a otp development tools

s3c8639/c863a/p863a/c8647/f8647 clock circuit 7 - 1 7 clock circuit overview the clock frequency generated for s3c8639/c863a/c8647 by an external crystal range s from 8 mhz to 1 2 mhz. the maximum cpu clock frequency is 1 2 mhz. the x in and x out pins connect the external oscillator or clock source to the on-chip clock circuit. system clock circuit the system clock circuit has the following components: ? external crystal or ceramic resonator oscillation source (or an e xternal clock source) ? oscillator stop and wake-up functions ? programmable frequency divider for the cpu clock (f osc divided by 1, 2, 8, or 16) ? system clock control register, clkcon s3c8639/c863a/c8647 x in x out c1 c2 figure 7-1. main oscillator circuit (external crystal or ceramic resonator)
clock circuit s3c8639/c863a/p863a /c8647/f8647 7 - 2 clock status during power-down modes the two power-down modes, stop mode and idle mode, affect the system clock as follows: ? in stop mode, the main oscillator is halted. stop mode is released and the os ci l l ator is started by a reset operation or an external interrupt (with rc delay noise filter). ? in idle mode, the internal clock signal is gated to the cpu, but not to interrupt structure, timers and timer/ counters, and the iic-bus interface functions. idle mode is released by a reset or by an external or internal interrupt. main osc noise filter oscillator wake-up oscillator stop clkcon.7 int pin (1) stopcon notes: 1. an external interrupt (with rc-delay noise filter) can be used to release stop mode and "wake up" the main oscillator. in s3c8639/c863a/c8647, the p0.0-p0.2 and external interrupts are of this type. 2. for s3c8639/c863a/c8647, the clkcon signature code (clkcon.0-clkcon.2) should not be '101b' (because no subsystem clock is implemented). clkcon.3,.4 1/2 1/8 1/16 m u x clkcon.0-.2 3-bit signature code (2) m u x cpu clock clkcon.5,.6 stop instruction figure 7-2. system clock circuit diagram
s3c8639/c863a/p863a/c8647/f8647 clock circuit 7 - 3 system clock control register (clkcon) the system clock control register, clkcon, is located in set 1, address d4h. it is read/write addressable and has the following functions: ? oscillator irq wake-up function enable/disable ? main oscillator stop control ? oscillator frequency divide-by value ? system clock signal selection the clkcon register controls whether or not an external interrupt can be used to trigger a power down mode release. (this is called the "irq wake-up" function.) the irq wake-up enable bit is clkcon.7. after a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the f osc /16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can raise the cpu clock speed to f osc , f osc /2, or f osc /8. for the s3c8639/c863a/c8647 microcontroller s , the clkcon.2?clkcon.0 system clock signature code must be any value other than " 101b " . (the " 101b " setting is invalid because a subsystem clock is not implemented.) the reset value for the clock signature code is " 000b " and should remain so during the normal operation. system clock selection bits: 101b = invalid selection others = normal operating mode lsb msb system clock control register (clkcon) d4h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 divide-by selection bits for cpu clock frequency: 00 = f osc /16 01 = f osc /8 10 = f osc /2 11 = f osc (non-divided) main oscillator stop control bits: 00 = no effect 01 = no effect 10 = stop main oscillator 11 = no effect oscillator irq wake-up enable bit: 0 = enable irq for main system oscillator wake-up function in power down mode 1 = disable irq for main system oscillator wake-up function in power down mode figure 7-3. system clock control register (clkcon)
clock circuit s3c8639/c863a/p863a /c8647/f8647 7 - 4 notes
s3c8639/c863a/p863a/c8647/f8647 reset reset and power-down 8- 1 8 reset reset and power-down system reset overview during a power-on reset, the voltage at v dd goes to high level and the reset pin is forced to low level. the reset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this procedure brings s3c8639/c863a/c8647 into a known operating status. to spare time for internal cpu clock oscillation to stabilize, the reset pin must be held to low level for a minimum time interval after the power supply comes within tolerance. the minimum required time for oscillation stabilization in a reset operation is 1 millisecond. whenever a reset occurs during the normal operation (that is, when both v dd and reset are at high level), the reset pin is forced low and the reset operation starts. all system and peripheral control registers are then reset to their default hardware values (see tables 8-1, 8-2, and 8-3). in summary, the following sequence of events occurs during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? ports 0?3 are set to input mode. ? peripheral control and data registers are disabled and reset to their default hardware values. ? the program count er (pc) is loaded with the program reset address in the rom, 0100h. ? when the programmed oscillation stabilization time interval has elapsed, the instruction stored in the rom location 0100h (and 0101h) is fetched and executed. note to program the duration of the oscillation stabilization interval, you should make the settings appropriate to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing "1010b" to the upper nibble of btcon.
reset reset and power-down s3c8639/c863a/p863a/c8647/f8647 8- 2 hardware reset values tables 8-1, 8-2, and 8-3 list the reset values for cpu and system registers, peripheral control registers, and peripheral data registers after a reset operation. the following notation is used to represent reset values: ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an "x" means that the bit value is undefin ed after a reset. ? a dash ("?") means that the bit is either not used or not mapped. table 8-1. set 1 register values after reset register name mnemonic address bit values after reset dec hex 7 6 5 4 3 2 1 0 timer m0 counter register tm0cnt 208 d0h 0 0 0 0 0 0 0 0 timer m0 data register tm0data 209 d1h 0 0 0 0 0 0 0 0 timer m0 control register tm0con 210 d2h 0 0 0 0 0 0 0 0 basic timer control register btcon 211 d3h 0 0 0 0 0 0 0 0 clock control register clkcon 212 d4h 0 0 0 0 0 0 0 0 system flags register flags 213 d5h x x x x x x 0 0 register pointer 0 rp0 214 d6h 1 1 0 0 0 ? ? ? register pointer 1 rp1 215 d7h 1 1 0 0 1 ? ? ? stack pointer (high byte) sph 216 d8h x x x x x x x x stack pointer (low byte) spl 217 d9h x x x x x x x x instruction pointer (high byte) iph 218 dah x x x x x x x x instruction pointer (low byte) ipl 219 dbh x x x x x x x x interrupt request register irq 220 dch 0 0 0 0 0 0 0 0 interrupt mask register imr 221 ddh x x x x x x x x system mode register sym 222 deh 0 ? ? x x x 0 0 page pointer register pp 223 dfh 0 0 0 0 0 0 0 0 notes : 1. as the sym register is not used for s3c8639/c863a/c8647, sym.5 should always be "0". if you accidentally write a ?1? to this bit during the normal operation, a system malfunction may occur. 2. except for tm0cnt, tmodata, and irq, all registers in set 1 are read/write addressable. 3. you cannot use a read-only register as a destination field for the instructions or, and, ld, and ldb . the read-only registers in the s3c8639/c863a/c8647 register file are: tm0cnt, tm0data, irq, syncrd, tm1cnth, tm1cntl, tm1datah, tm1datal, addata, btcnt, pwmcnt, and rbdr. 4. interrupt pending flags that must be cleared by software are noted by shaded table cells.
s3c8639/c863a/p863a/c8647/f8647 reset reset and power-down 8- 3 table 8-2. set 1, bank 0 register values after reset register name mnemonic address bit values after reset dec hex 7 6 5 4 3 2 1 0 port 0 data register p0 224 e0h 0 0 0 0 0 0 0 0 port 1 data register (note) p1 225 e1h ? ? ? ? ? 0 0 0 port 2 data register p2 226 e2h 0 0 0 0 0 0 0 0 port 3 data register p3 227 e3h 0 0 0 0 0 0 0 0 port 0 control register (high byte) p0conh 228 e4h 0 0 0 0 0 0 0 0 port 0 control register (low byte) p0conl 229 e5h 0 0 0 0 0 0 0 0 port 1 control register (note) p1con 230 e6h ? ? 0 0 0 0 0 0 port 2 control register (high byte) p2conh 231 e7h 0 0 0 0 0 0 0 0 port 2 control register (low byte) p2conl 232 e8h 0 0 0 0 0 0 0 0 port 3 control register (high byte) p3conh 233 e9h 0 0 0 0 0 0 0 0 port 3 control register (low byte) p3conl 234 eah 0 0 0 0 0 0 0 0 port 0 external interrupt control register p0int 235 ebh ? 0 0 0 ? 0 0 0 watchdog time control register wdtcon 236 ech ? ? ? ? 0 0 0 0 sync control register 0 syncon0 237 edh 0 0 0 0 0 0 0 0 sync control register 1 syncon1 238 eeh 0 0 0 0 0 0 0 0 sync control register 2 syncon2 239 efh 0 0 0 0 0 0 0 0 sync port read data register syncrd 240 f0h ? ? ? ? 0 0 0 0 note: not used for the s3c8647.
reset reset and power-down s3c8639/c863a/p863a/c8647/f8647 8- 4 table 8-2. set 1, bank 0 register values after reset (continued) register name mnemonic address bit values after reset dec hex 7 6 5 4 3 2 1 0 timer m1 counter register high tm1cnth 241 f1h ? ? ? ? 0 0 0 0 timer m1 counter register low tm1cntl 242 f2h 0 0 0 0 0 0 0 0 timer m1 data register high tm1datah 243 f3h ? ? ? ? 0 0 0 0 timer m1 data register low tm1datal 244 f4h 0 0 0 0 0 0 0 0 timer m1 control register tm1con 245 f5h 0 0 0 0 0 0 0 0 timer m2 control register tm2con 246 f6h 1 1 1 1 1 0 0 0 a/d converter control register adcon 247 f7h ? 0 0 0 0 0 0 0 a/d converter data register addata 248 f8h x x x x x (4) x (4) x (4) x (4) pseudo hsync generation register phgen 249 f9h 0 1 0 1 0 0 1 1 pseudo vsync generation register pvgen 250 fah 0 1 0 1 0 0 1 1 stop control register stopcon 251 fbh 0 0 0 0 0 0 0 0 location fch is not mapped. basic timer counter register btcnt 253 fdh 0 0 0 0 0 0 0 0 external memory timing register emt 254 feh 0 1 1 1 1 1 0 ? interrupt priority register ipr 255 ffh x x x x x x x x notes: 1. except for syncrd, tm1cnth, tm1cntl, tm1datah, tm1datal, addata, and btcnt, all registers in set 1, bank 0 are read/write addressable. 2. you cannot use a read-only register as a destination field for the instructions or, and, ld, and ldb. the read-only registers in the s3c8639/c863a/c8647 register file are: tm0cnt, tm0data, irq, syncrd, tm1cnth, tm1cntl, tm1datah, tm1datal, addata, btcnt, pwmcnt, and rbdr. 3. interrupt pending flags that must be cleared by software are no ted by shaded table cells. 4. not mapped for the s3c8647.
s3c8639/c863a/p863a/c8647/f8647 reset reset and power-down 8- 5 table 8-3. set 1, bank 1 register values after reset register name mnemonic address bit values after reset dec hex 7 6 5 4 3 2 1 0 pwm 0 data register pwm0 224 e0h 0 0 0 0 0 0 0 0 pwm 1 data register pwm1 225 e1h 0 0 0 0 0 0 0 0 pwm 2 data register pwm2 226 e2h 0 0 0 0 0 0 0 0 pwm 3 data register pwm3 227 e3h 0 0 0 0 0 0 0 0 pwm 4 data register pwm4 228 e4h 0 0 0 0 0 0 0 0 pwm 5 data register pwm5 229 e5h 0 0 0 0 0 0 0 0 pwm 6 data register (4) pwm6 230 e6h 0 0 0 0 0 0 0 0 pwm control register pwmcon 231 e7h 0 0 0 ? ? ? ? ? pwm counter register pwmcnt 232 e8h 0 0 0 0 0 0 0 0 ddc control register dcon 233 e9h ? ? ? ? 1 0 0 0 ddc address register 0 dar0 234 eah 1 0 1 0 ? ? ? ? ddc clock control register dccr 235 ebh 0 0 0 0 1 1 1 1 ddc control/status register 0 dcsr0 236 ech 0 0 0 0 0 0 ? 0 ddc control/status register 1 dcsr1 237 edh ? ? ? ? ? 0 1 0 ddc address register 1 dar1 238 eeh x x x x x x x ? transmit prebuffer data register tbdr 239 efh x x x x x x x x receive prebuffer data register rbdr 240 f0h x x x x x x x x ddc data shift register ddsr 241 f1h x x x x x x x x slave iic-bus control/status register (4) sicsr 242 f2h 0 0 0 0 0 0 0 0 slave iic-bus address register (4) siar 243 f3h x x x x x x x ? slave iic-bus data shift register (4) sidsr 244 f4h x x x x x x x x locations f5h?ffh are not mapped. notes : 1. except for pwmcnt and rbdr, all registers in set 1, bank 1 are read/write addressable. 2. you can not use a read-only register as a destination field for the instructions or, and, ld, and ldb. the read-only registers in the s3c8639/c863a/c8647 register file are: tm0cnt, tm0data, irq, syncrd, tm1cnth, tm1cntl, tm1datah, tm1datal, addata, btcnt, pwmcnt, and rbdr. 3. interrupt pending flags that must be cleared by software are noted by shaded table cells. 4. not used for the s3c8647.
reset reset and power-down s3c8639/c863a/p863a/c8647/f8647 8- 6 power-down modes stop mode stop mode is invoked by the instruction stop (opcode 7fh) and the stop control register (stopcon). in stop mode, the operation of the cpu and all peripherals is halted. that is, the on-chip main oscillator stops and the supply current is reduced to less than 5 m a. all system functions stop when the clock "freezes," but data stored in the internal register file is retained. stop mode can be released in one of two ways: by a reset or by an external interrupt (with rc delay). note do not use stop mode if you are using an external clock source as x in input must be restricted internally to v ss to reduce current leakage. using reset reset to release stop mode stop mode is released when the reset signal goes active (high level): all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. a reset operation automatically selects a slow clock (1/16) because clkcon.3 and clkcon.4 are cleared to "00b". after the programmed oscillation stabilization interval has elapsed, the cpu starts the system initialization routine by fetching the program instruction stored in the rom location 0100h (and 0101h). using an external interrupt to release stop mode only external interrupts with an rc-delay noise filter circuit can be used to release stop mode. which interrupt you can use to release stop mode in a given situation depends on the microcontroller's current internal operating mode. the external interrupts in the s3c8639/c863a/c8647 interrupt structure that can be used to release stop mode are: ? external interrupts p0.0 (int0), p0.1 (int1 ), and p0.2 (int2) ? timer m0 capture interrupt in capture mode (with rising or falling edge trigger at the tm0cap pin and vsync-o from sync-processor.) please note the following conditions for stop mode release: ? if you release stop mode using an external interrupt, the current values in system and peripheral control registers are unchanged. ? if you use an external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the control and clock settings appropriate before entering stop mode. ? if you use an interrupt to release stop mode, the clkcon.4 and clkcon.3 bit-pair setting remains unchanged and the currently selected clock value is used. ? the external interrupt is serviced when the stop mode release occurs. following the iret from the service routine, the instruction right next to the one that initiated stop mode is executed.
s3c8639/c863a/p863a/c8647/f8647 reset reset and power-down 8- 7 idle mode idle mode is invoked by the instruction idle (opcode 6fh). in idle mode, cpu operations are halted while some peripherals remain active. in idle mode, the internal clock signal is gated away from the cpu, but all peripherals timers remain active. port pins retain the mode (input or output) they had at the time idle mode was entered. there are two ways to release idle mode: 1. execute a reset. all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects a slow clock (1/16) because clkcon.4 and clkcon.3 are cleared to "00b". if interrupts are masked, a reset is the only way to release idle mode. 2. activate any enabled interrupt, causing idle mode to be released. when you use an interrupt to release idle mode, the clkcon.4 and clkcon.3 register values remain unchanged, and the currently selected clock value is used. the interrupt is then serviced. when the return-from-interrupt (iret) occurs, the instruction right next to the one that initiated idle mode is executed. note only external interrupts can be used to release stop mode. to release idle mode, you can use either an internally-generated or externally-generated interrupt.
reset reset and power-down s3c8639/c863a/p863a/c8647/f8647 8- 8 f f programming tip ? sample s3c8639/c863a/c8647 initialization routine the following sample program shows you how to make initial settings for the s3c8639/c863a/c8647 address space, interrupt vectors, and peripheral functions. program comments guide you through the steps: ; << base number set ting >> decimal ; << definition >> tm0_reg equ 40h org 0000h ; << interrupt vector addresses >> org 00ech vector tm0_ovf_int ; irq0 vector tm0_cap_int ; irq0 vector tm2 _int ; irq1 vector tm1_ovf_int ; irq2 vector tm1_cap_int ; irq2 vector ddc_int ; irq3 vector p00_int ; irq4 vector p01_int ; irq5 vector p02_int ; irq6 vector siic_int ; irq7 (used only s3c863x) ; << initialize system and peripherals >> org 0100h ; reset address ld btcon,#0a0h ; disable watchdog timer ld clkcon,#10h ; select divided-by-tw o oscillator frequency as cpu clock ; enable irq for main system oscillator wake-up ; < system register settings > clr sym ; disable fast interrupts; global interrupt disable clr emt ; no access wait time; select internal stack area ld sph,#00h ; set stack pointer (stack starts from #0ffh) ; < interrupt settings > ld ipr,#8fh ; set interrupt priorities as follows: ; irq3 > irq2 > irq1 > irq0 ld imr,#0fh ; enable irq levels 0, 1, 2, and 3 ; < timer m0 settings > ld tm0con,#8fh ; enabl e timer m0 overflow and capture interrupts
s3c8639/c863a/p863a/c8647/f8647 reset reset and power-down 8- 9 f f programming tip ? sample s3c8639/c863a/c8647 initialization routine (continued) ini_peri_set: sb0 ; select bank 0 ld p0conh,#0ffh ; set port 0 high byte to push-pull output mode ld p0conl,#0ffh ; set port 0 low byte to push-pull output mode ld p0int,#00h ; disable p0.0, p0.1 and p0.2 external interrupts ; ld p1con,#00h ; set p1.0?p1.2 to input mode ld p2conh,#0ffh ; set port 2 high byte to n-channel open-drain pwm ; output mode ld p2conl,#0ffh ; set port 2 low byte to push-pull pwm output mode ld p3conh,#0aah ; set port 3 high byte to push-pull output mode ld p3conl,#0aah ; set port 3 low byte to push-pull output mode ; < timer m1 settings > ld tm1con,#2ch ; enable timer m1 capture and overflow interrupt, timer m1 ; clock source is hsynci from sync processor ; < timer m2 settings > ld tm2con,#3dh ; enable timer m2 capture and overflow interrupt ; < sync processor settings > ld syncon0,#20h ; 5 bit counter capture mode ld syncon1,# 80h ; set negative polarity (500 ns at 8 mhz) for clampo ld syncon2,#0a0h ; pseudo sync output ; < pwm settings > sb1 ; select bank 1 ld pwmcon,#20h ; start pwm counter, pwm counter clock is f osc ; < ddc tx/rx interface settings > ld dcon,#0ah ; select ddc1 tx mode ld dccr,#0a3h ; enable ddc interrupt, ddc clock is 100 khz ; << initialize data registers >> sb0 ; select bank 0 srp #0c0h ; set register pointer ; < clear all data registers from 00h to ffh > ld r0,#0ffh ; enable timer m2 interrupt ramclr: clr @r0 ; page 0 ram clear djnz r0,ramclr
reset reset and power-down s3c8639/c863a/p863a/c8647/f8647 8- 10 f f programming tip ? sample s3c8639/c863a/c8647 initialization routine (continued) ; < initialize other registers > ei ; you must execute an ei instruction in this position ; in the initialization routine to enable servicing of ; external interrupts ; << main loop >> main: nop ; start main loop call key_scan ; sub-program module call led_display ; sub-program module call job ; sub-program module jr t,main ; f or main loop ; < subroutines > key_scan: nop ret led_display: nop ret job: nop ret
s3c8639/c863a/p863a/c8647/f8647 reset reset and power-down 8- 11 f f programming tip ? sample s3c8639/c863a/c8647 initialization routine (concluded) ; << interrupt service routines >> p00_int: push rp0 ; save old rp0 value srp0 #60h ; set rp0 for p0.0 interrupt service routine pop rp0 ; restore the rp0 value iret ; return from the interrupt ddc_int: push rp0 ; save old rp0 value srp0 #50h ; set rp0 for iic-bus interrupt service routine sb1 and ddcr, #11101111b ; clear ddc interrupt pending bit sb0 pop rp0 ; restore the rp0 value iret ; return from the interrupt tm0_cap_int: push rp0 ; save old rp0 value srp #tm0_reg ; tm0_reg value should be defined pop rp0 ; restore the rp0 value iret ; return from the interrupt end
reset reset and power-down s3c8639/c863a/p863a/c8647/f8647 8- 12 notes
s3c8639/c863a/p863a/c8647/f8647 i/o ports 9- 1 9 i/o ports overview the s3c8639/c863a/c8647 microcontroller s have four i/o ports with a total of 27 pins. and the s3c8647 microcontroller has three i/o port 0 with a total of 19 pins. each port can be flexibly configured to meet application design requirements. the cpu accesses ports by directly writing or reading port registers. no special i/o instructions are required. table 9-1 gives you an overview of port functions: table 9-1. s3c8639/c863a/c8647 port configuration overview port configuration options programmability 0 8-bit general i/o port. alternatively used for external interrupt inputs and for timer m 0 input function . bit programmable 1 (only s3c863x) 3 -bit i/o port for normal i/o or n-channel open drain output. alternatively used for iic-bus clock and data i/o. bit programmable 2 8-bit i/o port for normal i/o , pwm push-pull outputs , pwm n-channel open-drain outputs with 5-volt load capability , or csync signal input . bit programmable 3 8-bit general i/o port. a lternatively used as n-channel open-drain , push-pull outputs with 5-volt load capability or for normal input with pull-up resistor. multiplexed for alternative use as a/d converter inputs, ad0?ad3. bit programmable
i/o ports s3c8639/c863a/p863a /c8647/f8647 9- 2 port data registers data registers for ports 0?3 have the format shown in figure 9-1. table 9-2 gives you an overview of the port data register locations: table 9-2. port data register summary register name mnemonic decimal hex location r/w port 0 data register p0 224 e0h set 1, bank 0 r/w port 1 data register (only s3c863x) p1 225 e1h set 1, bank 0 r/w port 2 data register p2 226 e2h set 1, bank 0 r/w port 3 data register p3 227 e3h set 1, bank 0 r/w pn.4 pn.3 i/o port data register format (n = 0-3) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb pn.1 pn.2 pn.5 pn.6 pn.7 pn.0 note: port 1 is a 3-bit port. only bits p1.2-p1.0 of the port 1 data register are mapped. all the other s3c8639/c863a i/o ports are 8-bit. figure 9-1. port data register format port 0 port 0 is an 8-bit i/o port with individually configurable pins. you can directly access port 0 pins by writing or reading the port 0 data register, p0 (set 1, bank 0, e0h). you can use port 0 for general i/o, or for the following alternative functions: ? low-byte pins (p0.3 ?p0.0) can be configured as push-pull outputs , while p0.2?p0.0 as a multiplexed input pins for external interrupts int2?int0 with rising or falling edge detection. ? high-byte pins (p0.7 ?p0.4) can be configured as multiplexed inputs and push-pull outputs. p0.4 can serve as the timer m 0 capture input pin (t m 0cap). two 8-bit control registers are used to configure port 0 pins: p0conh (set 1, bank 0, e 4 h) for p0.7?p0.4 and p0conl (set 1, bank 0, e 5 h) for p0.3?p0.0. each byte contains four bit-pairs and each bit-pair configures one pin. the low-byte port 0 control register, p0conl, is also used to enable and disable the external interrupts, int2?int0, at pins p0.2?p0.0, respectively.
s3c8639/c863a/p863a/c8647/f8647 i/o ports 9- 3 port 0 high-byte control register (p0conh) the four bit-pairs in the port 0 high-byte control register, p0conh, have the following functions: ? to configure individual port 0 pins to multiplexed input mode or push-pull output mode. ? to configure alternative input or output functions for p0.7 ?p0.4. bit-pair 1/0 configures the capture signal input pin for timer m0 at p0.4. port 0 control register, high byte (p0conh) e4h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.7 (note) normal input mode multiplexed input mode (tm0cap) push-pull output mode p0conh pin configuration settings: 00 01 1x p0.6 (note) p0.5 (note) p0.4/tm0cap note: not used for the s3c8647. figure 9-2. port 0 high-byte control register (p0conh)
i/o ports s3c8639/c863a/p863a /c8647/f8647 9- 4 port 0 low-byte control register (p0conl) the low-byte port 0 pins, p0.3?p0.0 can be configured individually as inputs or as push-pull outputs. you can alternatively configure the pins p0.2?p0.0 as external interrupt inputs with rising or falling edge detection. port 0 control register, low byte (p0conl) e5h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.3 (note) normal input mode input mode, rising edge interrupt detection input mode, falling edge interrupt detection push-pull output mode p0conl pin configuration settings: 00 01 10 11 p0.2/int2 p0.1/int1 p0.0/int0 note: not used for the s3c8647. figure 9-3. port 0 low-byte control register (p0conl)
s3c8639/c863a/p863a/c8647/f8647 i/o ports 9- 5 port 0 external interrupt control register (p0int) the port 0 external interrupt control register, p0int, is used to enable and disable the external interrupts int2? int0 at p0.2?p0.0, respectively, and also to detect and clear external interrupt pending conditions at these pins. to selectively enable the external interrupts int0, int1, and int2, you set p0int.0, p0int.1, and p0int.2 to ?1?, respectively. the application program can poll the corresponding interrupt pending bits ? p0int.4 for int0, p0int.5 for int1, and p0int.6 for int2 ? to detect external interrupt pending conditions. after an external interrupt has been serviced, the service routine must clear the pending condition by writing a ?0? to the appropriate pending bit. writing a ?1? to the pending bit has no effect. port 0 external interrupt control register (p0int) ebh, set 1, bank 0, r/w - .6 .5 .4 - .2 .1 .0 msb lsb not used for s3c8639/c863a/c8647 no interrupt pending (when read) clear pending condition (when write) interrupt is pending (when read) no effect (when write) p0.2-p0.0 interrupt pending flags 0 0 1 1 interrupt pending flags for p0.2-p0.0 not used for s3c8639/c863a/c8647 disable interrupt enable interrupt p0.2-p0.0 interrupt enable bits 0 1 interrupt enable bit for p0.2-p0.0 figure 9-4. port 0 external interrupt control register (p0int)
i/o ports s3c8639/c863a/p863a /c8647/f8647 9- 6 port 1 ( only s3c863x) port 1 is an 3 -bit port with individually configurable pins. you can directly access it by writing or reading the port 1 data register, p1 (set 1, bank 0, e1h). you can use port 1 for normal output , input mode , or n-channel open- drain output mode . the port 1 control register, p1con (set 1, bank 0, e6h) is used to configure port 1 pins. each byte contains four bit-pairs and each bit-pair configures one pin. bit pair 3/2 configures the iic-bus clock pin for scl1 at p1.1. bit pair 1/0 controls p1.0 when it is set to "11b", the sda1 is enabled for iic-bus data pin. port 1 control register (p1con) e6h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used for s3c8639/c863a/c8647 input mode push-pull output mode n-channel open-drain output mode (5 v load capability) multiplexed mode (scl1/sda1) p1con pin configuration settings: 00 01 10 11 p1.2 p1.1/scl1 p1.0/sda1 figure 9-5. port 1 control register (p1con)
s3c8639/c863a/p863a/c8647/f8647 i/o ports 9- 7 port 2 port 2 is a n 8-bit i/o port with individually configurable pins. you can directly access port 2 pins by writing or reading the port 2 data register, p2 (set 1, bank 0, e2h). two 8-bit control registers are used to configure port 2 pins: p2conh (set 1, bank 0, e7h) which let you select digital input mode (or ttl input mode), normal or pwm push-pull output mode , or n-channel open drain pwm output mode. and you can select digital input mode, normal or pwm push-pull output mode at the p2conl (set 1, bank 0, e8h) port 2 control register, high byte (p2conh) e7h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p2.7/csync-l p2conh pin configuration settings: p2.6/pwm6 (note) p2.5/pwm5 p2.4/pwm4 0x ttl input mode (csync-l) 1x push-pull output mode bits 7,6 00 input mode 01 push-pull output mode 10 push-pull pwm output mode (5 v load capability) 11 n-channel open-drain pwm output mode (5 v load capability) bits 5-0 note: not used for the s3c8647. figure 9- 6 . port 2 high-byte control register (p2conh)
i/o ports s3c8639/c863a/p863a /c8647/f8647 9- 8 port 2 control register, low byte (p2conl) e8h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p2.3/pwm3 p2conl pin configuration settings: p2.2/pwm2 p2.1/pwm1 p2.0/pwm0 input mode push-pull output mode push-pull pwm output mode (5 v load capability) 0x 10 11 figure 9-7. port 2 low-byte control register (p2conl)
s3c8639/c863a/p863a/c8647/f8647 i/o ports 9- 9 port 3 port 3 is an 8-bit i/o port with individually configurable pins. you can directly access it by writing or reading the port 3 data register, p3 (set 1, bank 0, e3h). you can selectively configure p3 pins to input or output mode. in input mode, you can also select a/d converter input mode (p3.0?p3.3 only) or normal digital input mode (with or without pull-up resistor). output mode is push-pull mode or n-channel open-drain mode (p3.4?p3.7 only). two 8-bit control registers are used to configure port 3 pins: p3conh (e9h, set 1, bank 0) for p3.7?p3.4 and p3conl (set 1, bank 0, eah) for p3.3?p3.0. each byte contains four bit-pairs and each bit-pair configures one pin. port 3 control register, high byte (p3conh) e9h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p3.7 p3conh pin configuration settings: p3.6 p3.5 p3.4 input mode input mode with pull-up resistor push-pull output mode n-channel open-drain output mode (5 v load capability) 00 01 10 11 figure 9- 8 . port 3 high-byte control register (p3conh) port 3 control register, high byte (p3conl) eah, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p3.3/adc3 p3conl pin configuration settings: p3.2/adc2 p3.1/adc1 p3.0/adc0 input mode analog input mode push-pull output mode n-channel open-drain output mode 00 01 10 11 figure 9- 9 . port 3 low-byte control register (p3conl)
i/o ports s3c8639/c863a/p863a /c8647/f8647 9- 10 function-fixed port th ese i/o pins are used only for the input and output of video synchronization signals to the sync processor or ddc & iic-bus interface. t he horizontal and vertical sync signals can be monitored directly through the sync port read data register (syncrd). sync signal ports ? csync - i: composite (sog) synchronization input port (ttl level) ? hsync - i: horizontal synchronization input (ttl level) ? vsync - i: vertical synchro nization input and synchro clock (vclk) for ddc 1 (ttl level) ? hsync - o: horizontal synchronization output from the sync processor ? vsync - o: vertical synchronization output from the sync processor ? clamp - o: clamp signal output with programmable width from the sync processor ddc and iic-bus interface ports ? sda 0 : ddc and iic-bus interface serial data ? scl 0 : ddc and iic-bus interface serial clock sync port read data register (syncrd) f0h, set 1, bank 0, read-only .7 .6 .5 .4 .3 .2 .1 .0 msb lsb syncrd pin configuration settings: not use for s3c8639/c863a hsync-i low data high data 0 1 vsync-i hsync-o vsync-o figure 9-10. sync port read data register (syncrd)
s3c8639/c863a/p863a/c8647/f8647 i/o ports 9- 11 f f programming tip ? configuring i/o port pins to specification the following sample program shows you how to configure the s3c8639/c863a/c8647 i/o ports to specification. the program comments explain the effect of the settings: ? ? ? sb0 ; select bank 0 ld p0conh,#0ffh ; set port 0 high byte to push-pull output mode ld p0conl,#0d5h ; set p0.3 to push-pull output mode ; set p0.0 ?p0.2 to rising edge interrupt mode ld p0int,#0fh ; enable port 0 external interrupt ld p1con,#00h ; set port 1 to input mode ld p2conh,#3fh ; set port 2 high byte to pwm n-channel open-drain ; output mode (5-volt capability) and csync input mode ld p2conl,#0ffh ; set port 2 low byte to pwm push-pull output mode ld p3conh,#0aah ; set port 3 high byte to push-pull output mode ld p3conl,#55h ; set port 3 low byte to analog input mode ? ? ?
i/o ports s3c8639/c863a/p863a /c8647/f8647 9- 12 notes
s3c8639/c863a/p863a/c8647/f8647 basic timer 10- 1 10 basic timer overview s3c8639/c863a/c8647 has a default timer: an 8-bit basic timer. you can use the basic timer (bt) in two different ways: ? as a watchdog timer , i t provide s an automatic reset mechanism in the event of a system malfunction . ? s ignal s the end of the required oscillation stabilization interval after a reset or a stop mode release. the functional components of the basic timer block are: ? clock frequency divider (f osc divided by 4096, 1024, or 128) with multiplexer ? 8-bit basic timer counter, btcnt (set 1, bank 0, fdh, read-only) ? basic timer control register, btcon (set 1, d3h, read/write) ? watchdog timer control register, wdtcon (set 1, bank 0, ech, read/write)
basic timer s3c8639/c863a/p863a /c8647/f8647 10- 2 basic timer control register (btcon) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. it is located in set 1, address d3h, and is read/write addressable using r egister addressing mode. a reset clears btcon to " 00h " . this enables the watchdog function and selects a basic timer clock frequency of f osc /4096. to disable the watchdog function, you must write the signature code " 1010b " to the basic timer register control bits btcon.7?btcon.4. the 8-bit basic timer counter, btcnt (set 1, bank 0, fdh), can be cleared at any time during the normal operation by writing a "1" to btcon.1. to clear the frequency dividers for both the basic timer input clock and the timer m 0 clock (unless timer m 0 uses an external clock source), you should write a "1" to btcon.0. basic timer control register (btcon) d3h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb divider clear bit for bt and t0: 0 = no effect 1 = clear both dividers (basic timer, timer m0) basic timer/counter clear bit: 0 = no effect 1 = clear basic timer watchdog time enable bits: 1010b = disable watchdog function others = enable watchdog function basic timer input clock selection bits: 00 = f osc /4096 01 = f osc /1024 10 = f osc /128 11 = not used figure 10-1. basic timer control register (btcon)
s3c8639/c863a/p863a/c8647/f8647 basic timer 10- 3 watchdog time control register (wdtcon) the watchdog time control register, wdtcon, is used to generate various watchdog time and to select hsync output. it is located in set 1, bank 0, address ech, and is read/write addressable using register addressing mode. watchdog time control register (wdtcon) ech, set 1, bank 0, r/w - - - - .2 .1 .0 msb lsb watchdog time generation control bits: not use for s3c8639/c863a/c8647 000 001 010 011 100 101 110 111 t btovf t btovf /2 t btovf /3 t btovf /4 t btovf /5 t btovf /6 t btovf /7 t btovf /8 note: t btovf = (1/f osc ) x (divider count of basic timer input clock) x 256 .3 hsync-o divide enable bit: 0 = hsync-i (non-divide) 1 = hsync-i/2 figure 10-2. watchdog time control register (wdtcon)
basic timer s3c8639/c863a/p863a /c8647/f8647 10- 4 basic timer function description watchdog timer function you can program the basic timer overflow signal (btovf) to generate a reset by setting btcon.7?btcon.4 to any value other than " 1010b " (the " 1010b " value disables the watchdog function) . a reset clears btcon to " 00h " , automatically enabling the watchdog timer function. a reset also selects the cpu clock (as determined by the current clkcon register setting),divided by 4096, as the bt clock. a r eset whenever a basic timer counter overflow occurs. during the normal operation, the application program must prevent the overflow and the accompanying reset operation from occurring. to do this, the btcnt value must be cleared (by writing a "1" to btcon.1) at regular intervals. and you can generate the various watchdog time by setting wdtcon.2-wdtcon.0. if a system malfunction occurs due to circuit noise or some other error condition, the bt counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. in other words, during the normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, btcnt) is always broken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. oscillation stabilization interval timer function you can also use the basic timer to program a specific oscillation stabilization interval after a reset or when s top mode has been released by an external interrupt. in stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. the btcnt value then starts increasing at the rate of f osc /4096 (for reset), or at the rate of the preset clock source (for an external interrupt). when btcnt.4 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume the normal operation. in summary, the following events occur when stop mode is released: 1. during the s top mode, a power-on reset or an external interrupt occurs to trigger the s top mode release and oscillation starts. 2. if a power-on reset occurred, the basic timer counter would increase at the rate of f osc /4096. if an external interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows. 4. when a btcnt.4 overflow occurs, the normal cpu operation resumes.
s3c8639/c863a/p863a/c8647/f8647 basic timer 10- 5 note: in a power-on reset operation, the cpu is idle during the required oscillation stabilization interval when btcnt.4 is set after releasing from reset or stop mode, cpu clock starts. mux 1/4096 div 1 /128 f osc bit 0 basic timer control register (write '1010xxxxb' to disable) clear reset or stop data bus 8-bit basic counter (read-only) ovf reset r 1 /1024 bits 3, 2 bit 1 watchdog time control register figure 10- 3 . basic timer block diagram
basic timer s3c8639/c863a/p863a /c8647/f8647 10- 6 f f programming tip ? configuring the basic timer this example shows how to configure the basic timer to sample specifications: org 0100h reset di ; disable all interrupts sb0 ; select bank 0 ld btcon,#0aah ; disable the watchdog timer ld clkcon,#98h ; non-divided clock clr sym ; disable global and fast interrupts clr spl ; sta ck pointer low byte ? "0" ; stack area starts at 0ffh ? ? ? srp #0c0h ; set register pointer ? 0c0h ei ; enable interrupts ? ? ? main ld btcon,#a2h ; watchdog timer disable ; basic timer/counter clear ld btcon,# 52h ; enable the watchdog timer ; basic timer clock: f osc /4096 ; clear basic timer counter ld wdtcon,#03h ; watchdog time: t btovf /4 nop nop ? ? ? jp t,main ? ? ?
s3c8639/c863a/p863a/c8647/f8647 timer m 0 11 - 1 11 timer m0 overview the 8-bit timer m0 is for monitor application. timer m0 includes capture timer mode using the appropriate t m0 con setting . timer m0 has the following functional components: ? clock frequency divider (f osc divided by 128 or 8 ) with multiplexer ? 2-bit prescaler for the timer m0 input clock ? 8-bit counter (t m0 cnt ; set1, d0h, read-only ) and 8-bit reference data register (t m0 data ; set1, d1h, read- only ) ? timer m0 capture or overflow interrupt (irq0, vector e2h, e0h) generation ? timer m0 control register, t m0 con (set 1 , d2 h, read/write) function description capture timer function the t imer m0 module can generate two interrupt s: the t imer m0 capture interrupt (t m0 int ), and the timer m0 overflow interrupt (tm0ovf). t m0 int belongs to interrupt level irq 0 , and is assigned the separate vector address, e2 h. t m0ovf is interrupt level irq 0 , vector e0 h. the t m0 int and tm0ovf pending condition s are automatically cleared by hardware after they are serviced. in capture timer mode, a signal edge that is detected at the tm0cap pin opens a gate and loads the current counter value into the timer m0 data register (tm0data) . you can select rising or falling edge to trigger this operation. both kinds of timer m0 interrupts can be used in capture mode: the timer m0 overflow interrupt is generated whenever a counter overflow occurs; the timer m0 capture interrupt is generated whenever the counter value is loaded into the timer m0 data register. by reading captured data value in t m0 data , and assuming a specific value for the timer m0 clock frequency, you can calculate the internal time of the signal being input to the tm0cap pin or the vertical sync output signal being output from the sync-processor module.
timer m0 s3c8639/c8 63a/p863a/c8647/f8647 11 - 2 timer m0 control register (t m0 con ) you use the t imer m0 control register, t m0 con, to ? select the timer m0 operating mode ( capture mode ) ? select the t imer m0 input clock frequency ? clear the t imer m0 counter, t m0 cnt ? enable the t imer m0 overflow interrupt and timer m0 capture interrupt ? select a 2-bit prescaler value for the timer m0 input clock ? select the timer m0 capture input source t m0 con is located in set 1 , at address d2 h, and is read/write addressable using register addressing mode. a reset clears t m0 con to " 00h " . this sets t imer m0 to disable capture timer mode, selects an input clock frequency of f osc / 128 , and disables t imer m0 overflow and capture interrupt s . you can clear the t imer m0 counter at any time during the normal operation by writing a "1" to t m0 con. 2 . the timer m0 overflow interrupt (tm0ovf) is in the interrupt level irq0 and has the vector address e0h. when the timer m0 capture interrupt is disabled, the timer m0 overflow interrupt by clock (f osc ) is possible. when a timer m0 overflow interrupt occurs and is serviced by the cpu, the pending condition is cleared automatically by hardware. to enable the timer m0 capture interrupt (irq 0 , vector e2 h), you must write t m0 con. 1 to "1". there is no pending bit cleared by software or static read bit which is h/w pending. after the interrupt request is serviced, the pending condition is automatically cleared by hardware. timer m0 control register (tm0con) d2h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer m0 input clock selection bit: 0 = f osc /128 1 = f osc /8 timer m0 capture input selection bit: 0 = tm0cap input pin selection 1 = v-sync output path selection from sync-processor timer m0 capture interrupt enable bit: 0 = disable the timer m0 capture interrupt 1 = enable the timer m0 capture interrupt timer m0 capture mode selection bit: 0 = capture on rising mode 1 = capture on falling mode timer m0 overflow interrupt enable bit: 0 = disable the timer m0 overflow interrupt 1 = enable the timer m0 overflow interrupt 2-bit prescaler bits: 00 = no division 01 = divide by 2 10 = divide by 3 11 = divide by 4 timer m0 counter clear bit: 0 = no effect 1 = clear timer m0 counter (when write) note: when the captured value is #0ffh, the overflow interrupt does not occur. when the vlaue of capture is changed from #0ffh to #00h, the overflow interrupt always occurs. when the captured value is #00h, the overflow interrupt occurs in advance. figure 11-1 . timer m0 control register (t m0 con )
s3c8639/c863a/p863a/c8647/f8647 timer m 0 11 - 3 block diagram 8-bit counter (read-only) tm0cnt bit 3 tm0clr timer m0 data register (read-only) tm0data r clear bit 7 f osc /8 f osc /128 data bus 2-bit pre- scaler bits 6, 5 data bus irq0 (timer m0 capture) irq0 (timer m0 overflow) bit 1 tm0int bit 0 bit 4 tm0cap vsync-o from sync processor bit 2 ovint timer m0 control register figure 11-2 . timer m0 functional block diagram
timer m0 s3c8639/c8 63a/p863a/c8647/f8647 11 - 4 notes
s3c8639/c863a/p863a/c8647/f8647 timer m 1 12- 1 12 timer m1 overview the 12 -bit timer m1 is an 12 -bit timer/counter for monitor application. timer m1 offers capture/overflow timer mode using the appropriate t m1 con setting . timer m1 has the following functional components: ? clock frequency selector as the timer m1 clock (f osc divided by 512, 128, or 2, hsync-i or csync-i from sync- processor ) with multiplexer ? capture signal selector from v-synco (sync-processor) or the timer m2 interval time ? 12 -bit counter (t m1 cnt h, tm1cntl; set1, bank0, f1h, f2h, read-only ) and 12 -bit reference data register (t m1 data h, tm1datal; set1, bank0, f3h, f4h, read-only ) ? timer m1 capture or overflow interrupt (irq2, vector e8h, e6h) generation ? timer m1 control register, t m1 con (set 1 , bank0, f5 h, read/write) function description overflow timer function the timer m1 module generate s an overflow signal whenever the timer m1 counter overflow occurs. if you set the timer m1 overflow interrupt enable bit, tm1con.2, to "1", an interrupt is generated whenever an overflow state is detected. after the interrupt request is generated, the counter register value is cleared and counting resumes from "00h". the timer m1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. capture timer function the t imer m1 module can generate , the t imer m1 capture interrupt (t m1 int ). t m1 int belongs to interrupt level irq 2 , and is assigned the vector address, e8 h. in capture timer mode, a capture signal from vsync-o (sync-processor) or the timer m2 interval timer opens a gate and loads the current counter value into the timer m1 data register (tm1data) . you can select vsync-o or the timer m2 interval timer as the capture signal source to trigger this operation. by reading captured data value in t m1 data h and tm1datal, and assuming a specific value for the timer m1 clock frequency, you can calculate the frequency of the signal being input to the hsync-i or csync-i from sync- processor by capture signal.
timer m1 s3c8639/c8 63a/p863a/c8647/f8647 12- 2 timer m1 control register (t m1 con ) you use the t imer m1 control register, t m1 con, to ? select the capture signal source ? select the t imer m1 clock input ? clear the t imer m1 counter, t m1 cnt h and tm1cntl ? enable the t imer m1 capture and overflow interrupt ? clear the timer m1 capture interrupt pending bit ? select vsync-o capture edge as capture signal source (when tm1con.7 = "1" ) t m1 con is located in set 1, bank0 , at address f5 h, and is read/write addressable using register addressing m ode. the setting for bit-pair tm1con.0 and tm1con.1 selects the timer m1 counter clock input. the timer m1 capture and overflow interrupt (tm1int, tm1ovf) are in the interrupt level irq2, but has the different vector address (e8h, e6h respectively). tm1con.4 is the interrupt pending flag for the timer m1 capture interrupt. to clear a timer m1 interrupt pending condition, the interrupt service routine must write a " 0 " to tm1con.4 after the cpu has acknowledged the request. tm1con.3 is flag to clear the 12-bit timer m1 counter. tm1con.7 is flag to select the capture signal source (timer m2 interval time or vsync-o from sync-processor) and tm1con.6 is flag to select the capture edge as the vsync-o capture signal source. a reset operation clears tm1con to "00h", selecting the hsync-i or csync-l from sync-processor are the timer m1 clock and disabling the timer m1 capture and overflow interrupt.
s3c8639/c863a/p863a/c8647/f8647 timer m 1 12- 3 timer m1 control register (tm1con) f5h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer m1 capture signal source selection bit: 0 = signal from the timer m2 interval time 1 = vsync-o from sync-processor timer m1 clock input selection bits: 00 = hsync-l or csync-l from sync-processor 01 = f osc /2 10 = f osc /128 11 = f osc /512 vsync-o capture source edge selection bit (when tm1con.7=1): 0 = vsync-o rising edge from sync-processor 1 = vsync-o falling edge from sync-processor timer m1 overflow interrupt enable bit: 0 = disable the timer m1 overflow interrupt 1 = enable the timer m1 overflow interrupt timer m1 counter clear bit (when write): 0 = no effect 1 = clear timer m1 counter timer m1 capture interrupt enable bit: 0 = disable the timer m1 capture interrupt 1 = enable the timer m1 capture interrupt timer m1 capture interrupt pending bit: 0 = interrupt i snot pending (when read) 0 = clear the pending bit (when write) 1 = interrupt is pending (when read) 1 = no effect (when write) figure 12-1 . timer m1 control register (t m1 con )
timer m1 s3c8639/c8 63a/p863a/c8647/f8647 12- 4 block diagram 12-bit counter tm1cntl tm1cnth cap 8 tm1con.1-.0 f osc /512 mux (the tm1datal and tm1datah registers are read-only.) irq2 tm1con.2 f osc /128 f osc /2 hsync-i/csync-i from sync processor tm1con.3 4 (the tm1cntl and tm1cnth registers are read-only.) ovf tm1con.5 capture signal from timer m2 interval time (tm2con1,0) tm1con.7 tm1con.6 vsync-o from sync-processor clear clear 12 tm1con.4 tm1con.5 irq2 timer m1 data register tm1datal tm1datah figure 12-2 . timer m1 functional block diagram
s3c8639/c863a/p863a/c8647/f8647 timer m 2 13- 1 13 timer m2 overview the interval timer m2 is no-counter timer for monitor application. timer m2 offers interval timer mode using the appropriate t m1 con setting . timer m2 has the following functional components: ? 5-bit scaler by f osc /1000 for timer m2 interval source ? timer m1 capture interval time source selector (when tm1con.5 is "1") with 2-bit scaler ? timer m2 interval interrupt (irq1, vector e4h) generation ? timer m2 control register, t m2 con (set 1 , f6 h, read/write) function description interval timer function the timer m2 module generate s an interval interrupt whenever the tm2con.2 is "1". t m2 int belongs to the interrupt level irq 1 , and is assigned the separate vector address, e4 h. the t m2 int pending condition is automatically cleared by hardware when it has been serviced. timer m2 control register (t m2 con ) you use the t imer m2 control register, t m2 con, to ? select the interval time signal source by 5-bit scaler ? enable the t imer m2 interval interrupt ? select timer m1 capture interval time by 2-bit scaler (when tm1con.5 = "1" ) t m2 con is located in set 1 , bank0, at address f6 h, and is read/write addressable using register addressing mode. a reset operation clears tm2con to "f8h" (11111000b), thereby setting the 5-bit scaler value to be divided by 32.
timer m2 s3c8639/c8 63a/p863a/c8647/f8647 13- 2 timer m2 control register (tm2con) f6h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb 5-bit scaler bits: 00000 = no division 00001 = divide by 2 00010 = divide by 3 . . . 11111 = divide by 32 timer m1 capture interval time selection bits: 00 = timer m2 interval (bypass) 01 = timer m2 interval x 10 10 = timer m2 interval x 20 11 = timer m2 interval x30 timer m2 interval interrupt enable bit: 0 = disable the timer m2 interval interrupt 1 = enable the timer m2 interval interrupt notes: 1. when the timer m1 capture mode is enabled (tm1con.5 = "1"), the value of 5-bit or 2-bit scaler can be changed only in the timer m1capture interrupt routine. 2. when the timer m1 capture mode is disabled (tm1con.5 = "0"), the value of 5-bit scaler can be changed only in the timer m2 interval interrupt routine. figure 13-1 . timer m2 control register (t m2 con )
s3c8639/c863a/p863a/c8647/f8647 timer m 2 13- 3 block diagram timer m1 capture signal 2-bit scaler tm2con.1,.0 /10 divider 5-bit scaler tm2con.2 tm2con.7-.3 f osc /1000 irq1 (timer m2 interval interrupt) "00" "01" "10" "11" figure 13-2 . timer m2 functional block diagram
timer m2 s3c8639/c8 63a/p863a/c8647/f8647 13- 4 notes
s3c8639/c863a/p863a/c8647/f8647 analog to digital converter 14- 1 14 analog-to-digital converter overview the 8 -bit a/d converter (adc) module of s3c8639/c863a/c8647 employs successive approximation logic to convert analog levels entering one of the four input channels to equivalent 8 -bit digital values. the analog input level must lie between the v dd2 and v ss 2 values. the a/d converter has the following components: ? analog comparator with s uccessive approximation logic ? d/a converter logic (resistor string type) ? 8-bit adc control register (adcon) ? four multiplexed analog data input pins (adc0 ? adc 3 ) ? 8-bit a/d conversion data output register (ad data ) (s3c863x) ? 4 -bit a/d conversion data output register (ad data ) (s3c8647) ? 8 -bit digital input port ( alternatively, i/o port ) ? v dd2 and v ss 2 pins (s3c863x) function description to initiate an analog-to-digital conversion procedure, write the channel selection data in the a/d converter control register adcon to select one of the four analog input pins (adcn, n = 0 ?3 ) and set the conversion start or enable bit, adcon.0 . the read-write adcon register is located in set 1 , bank0, at address f7h. during the normal conversion, adc block initially set s the successive approximation register to 8 0h (approximate ly the half-way point of an 8 -bit register). this register is then updated automatically in each conversion step. the successive approximation block performs 8 -bit conversions for one input channel at a time. you can dynamically select different channels by manipulating the channel selection bit value ( adcon.5?.4 ) in the adcon register. to start the a/d conversion, you should set, adcon.0. when a conversion is completed, adcon.3, the end-of-conversion (eoc) bit, is automatically set to 1 and the result is dumped into the addata register where it can be read. the a/d converter then enters an idle state. remember to read the contents of addata before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note as the a/d converter does not include any sample-and-hold circuitry, it is very important to keep the fluctuation in the analog level at the adc0 ? adc 3 input pins to an absolute minimum during the conversion process . any change in the input level, perhaps due to noise, will invalidate the result. if the chip enters to stop or idle mode in conversion process, there will be a leakage current path in a/d block. you must use stop or idle mode after a/d converting operation is finished.
analog to digital converter s3c8639/c8 63a/p863a/c8647/f8647 14- 2 conversion timing the a/d conversion process requires 4 steps ( 8 clock edges) to convert each bit. therefore, a total of 48 clocks are required to complete an 10 -bit conversion . with an 8 mhz f osc clock frequency, one clock cyc l e is 1 m s (when adcon.2, .1 are "01") . if each bit conversion requires 4 clocks, the conversion rate is calculated as follows: start (4 clocks) + (4 clocks /bit n bit s) + eoc (4 clocks) = 4(n+2) clocks, 1 m s x 4(n+2) = 4(n+2) m s at 8 mhz where, n = 4 (s3c8647), 10 (s3c863x) a/d converter control register (adcon) the a/d converter control register, adcon, is located at address f7h in set 1 , bank0. it has four functions: ? analog input pin select ion (b its 4 ,5 and 6) ? end-of-conversion status detection (bit 3 ) ? clock source selection (bits 2 and 1) ? a/d operation start or enable (b it 0) after a reset, the adc0 pin is automatically selected as the analog data input pin, and the start bit is turned off. you can select only one analog input channel at a time. other analog input pins (adc0 ? adc 3 ) can be selected dynamically by manipulating the adcon.6?.4 bits. start or enable bit: 0 = disable operation 1 = start operation not used for the s3c8639/c863a/c8647 end-of conversion bit (read-only): 0 = conversion is not complete 1 = conversion is complete - .6 .5 .4 .3 .2 .1 .0 lsb msb a/d cconverter control register (adcon) f7h, set 1, bank 0, r/w (eoc bit is read-only) a/d input pin selection bits: 5 0 0 1 1 clock source select: f osc /16 f osc /8 f osc /4 f osc 0 1 0 1 0 0 1 1 4 0 1 0 1 6 0 0 0 0 a/d input pin adc0 (p3.0) adc1 (p3.1) adc2 (p3.2) adc3 (p3.3) not used others figure 14-1. a/d converter control register (adcon)
s3c8639/c863a/p863a/c8647/f8647 analog to digital converter 14- 3 internal reference voltage levels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must remain within the range of av ss ( v ss 2 ) to av ref (v dd 2 ). different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first conversion bit is always 1/2 v dd2 . block diagram input pins adc3-adc0 (p3.3-p3.0) clock select conversion result (addata f8h, set 1, bank 0) - + to adcon.3 (eoc flag) successive approximation logic & register analog comparator mux adcon.6-.4 ( analog input pin select) adcon.0 (adc enable) f osc /n adcon.2-.1 to data bus adcon.0 (adc enable) av ref (v dd2 ) av ss (v ss2 ) 8-bit d/a converter (s3c863x) 4-bit d/a converter (s3c8647) figure 14-2 . a/d converter functional block diagram a/d converter data register (addata) bit 7 bit 6 bit 5 bit 4 bit 3 (note) bit 2 (note) bit 1 (note) bit 0 (note) note: not mapped for the s3c8647.
analog to digital converter s3c8639/c8 63a/p863a/c8647/f8647 14- 4 table 14-1 . a/d converter electrical characteristics (s3c863x) (t a = ? 4 0 c to + 85 c, v dd = 3.0 v to 5 . 5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? 8 ? bit total accuracy v dd = 5 v conversion time = 5 m s ? ? 2 lsb integral linearity error ile av ref = 5 v ? 1 differential linearity error dle av ss = 0 v ? 1 offset error of top eot 1 2 offset error of bottom eob 0.5 2 conversion time ( 1 ) t con 8-bit conversion 48 n/f osc (3) , n = 1, 4, 8, 16 20 ? 170 m s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 1000 ? m w analog reference voltage av ref ? 2.5 ? v dd v analog ground av ss ? v ss ? v ss + 0.3 v analog input current i adin av ref = v dd = 5 v ? ? 10 m a analog block current ( 2 ) i adc av ref = v dd = 5 v ? 1 3 ma av ref = v dd = 3 v 0.5 1.5 ma av ref = v dd = 5 v when power down mode 100 500 na notes : 1. " conversion time " is the time required from the moment a conversion operation starts until it ends . 2. i adc is an operating current during the a/d conversion. 3. f osc is the main oscillator clock.
s3c8639/c863a/p863a/c8647/f8647 analog to digital converter 14- 5 table 14-2 . a/d converter electrical characteristics (s3c8647) (t a = ? 4 0 c to + 85 c, v dd = 4.0 v to 5 . 5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? ? 4 ? bit absolute accuracy (1) ? 4 bit conversion 24 x n/f osc (3) , n = 1, 4, 8, 16 ? ? 0.5 lsb conversion time (2) t con 3 ? ? us analog input voltage v ian ? v ss ? v dd v analog input impedance r an ? 2 ? ? m w notes: 1. excluding quantization error, absolute accuracy values are within 0.5 lsb. 2 . " conversion time " is the time required from the moment a conversion operation starts until it ends . 3 . f osc is the main oscillator clock.
analog to digital converter s3c8639/c8 63a/p863a/c8647/f8647 14- 6 notes
s3c8639/c863a/p863a/c8647/f8647 pulse w idth modulation 15- 1 15 pulse width modulat ion pwm module the s3c8639/c863a/c8647 microcontroller s include seven 8-bit pwm circuits, pwm0?pwm6. the s3c8647 microcontroller includes six 8-bit pwm circuits, pwm0?pwm5. the operation of all pwm circuits is controlled by a single control register, pwmcon. the pwm counter, a 8-bit incrementing counter, is used by the 8-bit pwm circuits. to start the counter and enable the pwm circuits, set pwmcon.5 to "1". if the counter is stopped, it retains its current count value . w hen restarted, it resumes counting from the retained count value. by modifying the prescaler value, you can divide the input clock by one (non-divided), two, three, or four. the prescaler output is the clock frequency of the pwm counter. the pwm counter overflows when it reaches "3 fh " , and then continues counting from zero.
pulse width modulation s3c8639/c863a/p863a /c8647/f8647 15- 2 pwm control register (pwmcon) the control register for the pwm module, pwmcon, is located in set 1, bank 1, at register address e7h. you use pwmcon bit settings to control the following functions in the 8 -bit: ? pwm counter operation: stop/start (or resume counting) a reset clears pwmcon to " 00h " , disabling all pwm functions. pwm control register (pwmcon) e7h, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used for s3c8639/c863a/c8647 pwm counter enable bit: 0 = stop the pwm counter 1 = start the pwm counter 2-bit prescaler for pwm counter clock: 00 = non-divided 01 = divide by 2 10 = divide by 3 11 = divide by 4 figure 15- 1. pwm control register (pwmcon)
s3c8639/c863a/p863a/c8647/f8647 pulse w idth modulation 15- 3 pwm0?pwm6 the s3c8639/c863a/c8647 microcontroller s include seven 8-bit pwm circuits, pwm0?pwm6. the s3c8647 microcontroller include six 8-bit pwm circuits, pwm0?pwm5. each 8-bit pwm data unit is comprised of a n 8-bit basic frame. the 8 -bit pwm circuits have the following components: ? 8-bit counter ? 8-bit comparators ? 8-bit pwm data registers (pwm0 ?pwm5, pwm6 (note) ) ? pwm output pins (pwm0 ?pwm 5, pwm6 (note) ) the pwm0?pwm6 circuits are controlled by the pwmcon register (set 1, bank 1, e7h). note: not used for the s3c8647. 8-bit counter (6-bit + 2-bit counter) x 7 pwm0-pwm5, pwm6 (note) output pins "1" when reg > counter "0" when reg < counter = 8 x 7 8 8-bit pwm 8-bit pwm 8-bit pwm 8-bit pwm0-pwm5, pwm6 (note) registers 8-bit pwm 8 8 data bus 2-bit p.s. pwmcon.5 f osc 8-bit pwm0-pwm5, pwm6 (note) registers note: not used for the s3c8647. figure 15- 2. block diagram for pwm0?pwm 6
pulse width modulation s3c8639/c863a/p863a /c8647/f8647 15- 4 pwm0?pwm6 function description all the seven 8-bit pwm circuits have an identical function and each has its own 8-bit data register and 8-bit comparator. each circuit compares a unique data register value to the 8-bit pwm counter. the pwm0?pwm6 data registers are located in set 1, bank 1, at locations e0h?e6h, respectively. these data registers are read/write addressable. by loading specific values into the respective data registers, you can modulate the pulse width at the corresponding pwm output pins, pwm0?pwm6. (pwm0?pwm6 correspond to port 2 pins p2.0?p2.6. ) the level at the output pins toggles high and low at a frequency equal to the counter clock, divided by 64 (2 6 ). the duty cycle of the 8-bit pwm pins ranges from 0% to 9 8 . 44 % ( 63 / 64 ), based on the corresponding data register values. to determine the output duty cycle of an 8-bit pwm circuit, its 8-bit comparator sends the output level high when the data register value is greater than the lower 8-bit count value. the output level is low when the data register value is less than or equal to the lower 8-bit count value. the output level at the pwm0?pwm6 pins remains at low level for the first 256 counter clocks. then, each pwm waveform is repeated continuously, at the same frequency and duty cycle, until one of the following three events occurs: ? the counter is stopped ? the counter clock frequency is changed ? a new value is written to the pwm data register staggered pwm outputs the pwm0?pwm6 outputs are staggered to reduce the overall noise level on the pulse width modulation circuits. if you load the same value to the pwm0?pwm6 data registers, a match condition (data register value is equal to the 8 -bit count value) will occur on the same clock cycle for all the seven 8-bit pwm circuits. for example, the pwm0 output is delayed by one-half of a counter clock, pwm1 output by one-half of a counter clock, pwm2 output by one-half of a counter clock, and so on for the subsequent clock cycles (see figure 15- 4). note: the s3c8647 microcontroller includes just six 8-bit pwm circuits, pwm0?pwm5.
s3c8639/c863a/p863a/c8647/f8647 pulse w idth modulation 15- 5 counter value (hex) 0h 40h counter clock pwmn = "0" 0c0h pwmn = "1" pwmn = 20 h pwmn = 3fh 6.4 us pwm cycle 100 ns 3.2 us 100 ns 80h notes: 1. a counter clock value of 8 mhz is assumed for all timing values. 2. 'n' = 0 to 6, for pwm0-pwm5, pwm6 (3) . 3. not used for the s3c8647. figure 15- 3. pwm waveforms for pwm0?pwm 6
pulse width modulation s3c8639/c863a/p863a /c8647/f8647 15- 6 0h (after reset ) 40h counter clock pwm0 pwm1 pwm2 pwm3 1/2 clock delay 1/2 clock delay 1/2 clock delay match occurs; pwm0 toggles to high level. figure 15- 4. pwm clock to pwm0?pwm 6 output delays
s3c8639/c863a/p863a/c8647/f8647 pulse w idth modulation 15- 7 pwm counter the pwm counter is a n 8-bit incrementing counter. the same 8-bit counter is used by all pwm circuits. to determine the pwm module's base operating frequency, the counter is compared to the pwm data register value. pwm data registers a reset operation disables all pwm output. the current counter value is retained when the counter stops. when the counter starts, counting resumes from the retained value. pwm clock rate the timing of the 8-bit output channel is based on the maximum 12 mhz cpu clock frequency. the 2-bit prescaler value in the pwmcon register determines the frequency of the counter clock . you can set pwmcon.6 and pwmcon.7 to divide the cpu clock frequency by one (non-divided), two, three, or four. as the maximum cpu clock rate for the s3c8639/c863a/c8647 microcontroller s is 12 mhz, the maximum base pwm frequency is 187.5 khz (12 mhz divided by 64 ). this assumes a non-divided cpu clock.
pulse width modulation s3c8639/c863a/p863a /c8647/f8647 15- 8 f f programming tip ? programming pwm0 to sample specifications this sample program executes a test of the pwm block. the program parameters are as follows: ? the oscillation frequency of the main crystal is 8 mhz ? pwm frequency is 125 khz reset: di ; disable global interrupts sb0 ; select bank 0 ? ? ? ld p2conh,#11111111b ; select n-channel open-drain pwm output ld p2conl,#11111111b ; select push-pull pwm output sb1 ; select bank 1 or pwmcon,#00100000b ; pwmcon.5 ? 1; start the counter ; pwm counter clock is f osc sb0 ; select bank 0 ei ; enable gl obal interrupts ? ? ? pwmstart: sb1 ; select bank 1 ld pwm0, #80h ; load pwm0 data sb0 ; select bank 0 ret
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 1 16 sync processor overview the s3c8639/c863a/c8647 multi-sync signal processor (sync processor) is designed to process horizontal (hsync) and vertical (vsync) signals that are input to a multi-sync monitor. the sync processor can perform the following functions: ? detect sync input signals (vsync-i, hsync-i, and csync-i, also called screen-on-green, or sog) ? output a programmable pseudo sync generation signal ? detect the polarity of sync input signals ? separate and output sync signals (hsync-o, vsync-o, and clamp-o) the sync processor circuits are controlled by three control registers: syncon0, syncon1, and syncon2. v sync separation syncon0 register setting controls the output path of the sync processor?s 5-bit counter. using the 5-bit counter, the sync processor can separate the vsync signal from composite (h+v) sync signal. the counter value increments when a high level sync signal is detected and decrements when a low level signal is detected. no overflow or underflow can occur. that is, the 5 -bit counter increments until it reaches the maximum value of 11111b and then stops or decrements until it reaches the minimum value of 00000b. you can select fosc/2 or fosc/3 as the counter?s clock input source. when syncon0.5 is "1", a high signal level is output to a multiplexer whenever the counter value reaches 11111b and a low level is output when the counter value reaches 00000b. the signal level remains constant when the counter value is less than 11111b or greater than 00000b. clamp signal output syncon1 register settings control clamp signal output and pulse width. clamp output can be completely inhibited, or it can be generated at two, four, or eight times fosc. you can specify the signal edge on which the selected clamp pulse width is to be output (?front porch? or ?back porch?). when syncon1.7?.6 is set to "00", the clamp signal output is inhibited. in this case the clamp signal level (clamp-o) can be either "low" (when syncon1.4 is set to "1") or "high" (when syncon1.4 is "0").
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 2 logic for detecting sync-on-green (sog) special logic in the sync processor block can compare hsync and csync input signals to detect sync-on-green (sog). the interrupt sog through csync-i port is detected automatically at the sog detection block. you can confirm to sog by means of reading syncon2.2 (sog detection bit). pseudo sync generator syncon2 settings (syncon2.4 = ?0?) control the pseudo hsync and vsync generation registers value (see figure 16.1 and 16.2). the polarity of these frequencies is always positive, with pulse width of 2us (eight fsync clock, when fsync is 4 mhz) and 6 x phgen periods, respectively. the pseudo sync generator supports factory testing of the sync processor block and also protects a system against the effect of unexpected signals in transition period while mode changing. pseudo hsync generation register (phgen) f9h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 lsb pseudo hsync generation bits: when syncon2.4 (generation pseudo h/vsync generation mode) = "0" - positive polarity only - pulse width: 2 us (eight fsync clock, when fsync is 4 mhz) - range: 15.68 khz (phgen = ffh) -400 khz (phgen = 10h) figure 16-1. pseudo hsync generation register (phgen) pseudo vsync generation register (pvgen) fah, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb when syncon2.4 (generation pseudo h/vsync generation mode) = "0" - positive polarity only - pulse width: 6 phgen periods - pvgen value must be in [2-255] range pseudo vsync generation bits: figure 16-2. pseudo vsync generation register (pvgen)
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 3 hsync & vsync polarity detection, unmixed hsync detection and hsync blanking the polarity of hsync & vsync signal input to hsync-i & vsync-i pin is automatically detected. if the hsync polarity is negative, syncon1.0 equals to "0". if the hsync polarity is positive, syncon1.0 equals to "1". this polarity detection bit (syncon1.0) may be not accurate when the sync level is not in a transitional condition. and if the vsync polarity is negative, syncon1.1 equals to ?1?. this polarity detection bit (syncon1.1) may be not accurate when the sync level is not in a transitional condition. in composite sync mode, if syncon2.7 is set to "1", the current period of checked hsync is stable, unmixed with vsync signal. if syncon2.7 is "0", the current period of checked hsync is mixed with vsync signal, in which case it is recommended not to calculate the sync frequency. in this mode, the hsync signal is automatically blanked during the vsync signal extraction period. table 16-1. vesa monitor timing standards & phgen/pvgen value standard hsync freq. [khz] standard vsync freq. [hz] resolution line num. [hf/vf] pseudo hf/(phgen) [khz] pseudo vf/(pvgen) [hz] 31.469 59.940 640 480 525 31.49 (127) 59.65 (66) 37.861 72.807 520 38.09 (105) 73.26 (65) 37.500 75.000 500 37.73 (106) 74.87 (63) 35.156 56.250 800 600 625 35.08 (114) 56.23 (78) 37.879 60.317 628 38.09 (105) 60.27 (79) 48.077 72.188 666 48.19 (83) 72.57 (83) reset value 46.875 75.000 625 47.06 (85) 75.41 (78) 35.522 43.479 1024 768 817 35.71 (112) 43.76 (102) 48.363 60.004 806 48.19 (83) 59.64 (101) 56.476 70.069 806 56.33 (71) 69.72 (101) 60.023 75.029 800 59.70 (67) 74.62 (100) 63.995 70.016 1152 864 914 63.49 (63) 70.23 (113) 77.487 85.057 911 76.92 (52) 85.09 (113) 75.000 75.000 1280 960 1000 75.47 (53) 75.47 (125) 63.974 60.013 1280 1024 1066 63.49 (63) 60.12 (132) 79.976 75.025 1066 80.00 (50) 75.18 (133) 75.000 60.000 1600 1200 1250 75.47 (53) 60.08 (157) 107.043 85.022 1259 108.11 (37) 85.52 (158) note: pseudo hsync frequency = fsync/phgen value pseudo vsync frequency = pseudo hsync frequency/(8 pvgen value)
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 4 sync processor control register 0 (syncon0) the sync processor control register 0, syncon0, is located in set 1, bank 0, at address edh. it is read/write addressable. syncon0 bits 4?0 hold the 5-bit counter value which is used for compare function. whenever a high signal level is detected, the count value is incremented by one until it reaches the maximum value of "11111b" (no overflow occurs). whenever a low signal level is detected, the count value is decremented by one until it reaches the minimum value of "00000b" (no underflow occurs). note when the composit sync is inputted, compare mode is also called vsync separation mode. in this mode, output to the multiplexer is enabled. when the counter value is "11111b", the output is high level; when the counter value is "00000b", the output is low level. whenever the counter value is less than ( < ) "11111b", or greater than ( > ) "00000b", the previous output level is retained. syncon0 settings also control the following sync processor functions: ? horizontal or composite sync input (hsync-i or csync-i) selection ? automatically enable hsync blanking or hsync signal bypass ? vsync port input or 5-bit counter compare mode ? select the clock source for vsync-o see figure 16-3 for a detailed description of syncon0 register settings. sync processor control register 0 (syncon0) edh, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb 5-bit compare counter value bits: high signal: increment until "11111b" low signal: decrement until "00000b" vsync-o output source selection bit (during vsync signal extraction period): 0 = select vsync-i port input (when separate sync input mode) 1 = select 5-bit compare output (when composite sync input mode) sync input selection bit: 0 = hsync-i 1 = csync-i hsync blanking enable bit: 0 = disable (hsync signal bypass) (when syncon0.5="0") 1 = enable automatically hsync blanking (during vsync signal extraction period) (when syncon0.5="1") figure 16-3. sync processor control register 0 (syncon0)
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 5 sync processor control register 1 (syncon1) the sync processor control register 1, syncon1, is located in set 1, bank 0, at address eeh. it is read/write addressable. using syncon1 settings, you can: ? generate a clock pulse for clamp signal output ? select ?front porch? or ?back porch? mode for clamp-o ? control clamp-o, vsync-o, and hsync-o status ? detect hsync & vsync polarity see figure 16-3 for a detailed description of syncon1 register settings. sync processor control register 1 (syncon1) eeh, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb clamp output signal generation bits (csg1,0): 00 = inhibit clamp signal output 01 = (f osc x 2) clock pulse (250 ns at 8 mhz f osc ) 10 = (f osc x 4) clock pulse (500 ns at 8 mhz f osc, 333 ns at 12 mhz f osc ) 11 = (fosc x 8) clock pulse (1 us at 8 mhz, 666 ns at 12 mhz) front/back porch clamp-o mode selection bit: 0 = output clamp signal after rising edge of hsync-i (front porch) 1 = output clamp signal after falling edge of hsync-i (back porch) hsync polarity detection bit: (2) 0 = negative 1 = positive vsync polarity detection bit: (1) 0 = negative 1 = positive hsync ouput status bit: 0 = do not invert (by pass) 1 = invert hsync-o signal vsync ouput status bit: 0 = do not invert (by pass) 1 = invert vsync-o signal clamp signal ouput status bit: 0 = negative polarity 1 = positive polarity notes: 1. to check hsync/vsync polarity, it uses 16 clocks of timer m2 (fx/1000). if the vsync polarity is changing, this bit will be updated after a typical delay of 2 ms, at 8 mhz f osc (1.33 ms at 12 mhz f osc ) 2. the syncon1.0 may not be accurate when the hsync-i is composite sync signal input. figure 16-4. sync processor control register 1 (syncon1)
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 6 sync processor control register 2 (syncon2) the sync processor control register 2, syncon2, is located in set 1, bank 0, at address efh. it is read/write addressable. using syncon2 settings, you can: ? detect mixed and unmixed hsync period in composite sync ? select the pseudo sync generation enable mode ? select the clock source for the 5-bit counter ? sync signal output disable or enable ? sog signal detection ? 5-bit up/down counter latch status changing detection ? v dd level selection for ttl sync input ports see figure 16-5 for a detailed description of syncon2 register settings. sync processor control register 2 (syncon2) efh, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb unmixed hsync detection bit (when syncon0.5 is "1", read only) 0 = mixed hsync period with vsync of composite sync input (1) 1 = unmixed hsync periods 5-bit counter source clock (fsync) input selection bit: 0 = f osc /3 (when f osc is 12 mhz) 1 = f osc /2 (when f osc is 8 mhz) * countable maximum hsync pulse width: 7.85 us (when fsync is 4 mhz) v dd level selection bit for ttl sync input ports (only s3c863x) 0 = when v dd is +5 v 1 = when v dd is +3 v 5-bit up/down counter latch status changing detection bit: (2) 0 = when the latch status is not changed or it writes "0" to this bit 1 = when the latch status changing is detected sog detection bit: 0 = no sog signal (when read) 0 = clear sog detection 5-bit counter (when write) 1 = csync-i is sog signal (to check sog presence, it uses 64 csync input edge signal) sync signal output disable bit: 0 = enable sync signal output 1 = inhibit sync signal otput (output level is low) pseudo sync generation disable bit: 0 = enable pseudo hsync/vsync generation (positive polarity only) 1 = normal sync-processor operation (by pass) notes: 1. the syncon2.7 is still cleared before read this bit or it has been in mixed hsync period. 2. the syncon2.1 can be used to check the presence of composite sync signal input not used for ks88c6332/c6348 (only "0") figure 16-5. sync processor control register 2 (syncon2)
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 7 5-bit up/down counter (syncon0.4-.0) clamp-o syncon2.5 hsync polarity detector vsync polarity detector 4-bit counter 3-bit up/down counter n.f. 8-bit scaler (pvgen) syncon2.4 pseudo vsync generator 1/8 8-bit scaler (phgen) pseudo hsync generator vsync-o syncon1.3 f osc /3 f osc /2 hsync-i syncon2.4 syncon0.7 csync-i syncon1.2 syncon1.4 clamp signal generator f osc /1000 to timer m0/timer m1 capture input hsync-o sog detection logic syncon2.2 hsync blanking polarity n.f. to 12-bit counter tm1 syncon1.5 syncon0.6 f sync v sync-i (vclk) port read ovf syncon0.5 data bus figure 16-6. sync processor block diagram
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 8 detecting sync signal input you can detect the presence of a sync signal in two ways ? directly or indirectly. the direct detection method can be implemented in read port. the indirect detection method is interrupt-driven and uses the s3c8639/c863a/c8647 sync processor hardware. these methods are explained in detail below. direct detection method by reading the input status directly on the sync input pins vsync-i, hsync-i, csync-i, you can detect the presence of the incoming sync for a corresponding output. to enable direct sync input detection, you set syncon0.5 to ?0? (for vsync-i), syncon0.7 to ?0? (for hsync-i), and syncon0.7 to ?1? (for csync-i). you then read the state of the input pin(s) over a period of time to detect transitions in the signal level(s). if a transition is detected, it can be assumed that a sync signal is present. indirect detection method to indirectly detect vertical sync input at the vsync-i pin, you use register settings to assign either the timer m0 capture interrupt to this pin. for indirect detection of horizontal or composite input at the hsync-i or csync-i pin, you use the timer 1 input clock source to generate a timer m1 capture/overflow interrupt by capture signal from timer m2 interval or vsync- o from sync-processor, when a signal level transition occurs. or to detect composite sync , you can confirm to presence with checking syncon2.1. (this bit is used to check the presence of composite sync signal input.) when the correct settings have been made, the application software polls for the respective interrupts to determine the presence of sync input signals, as follows: ? indirect vsync input detection check for the occurrence of a timer m0 capture interrupt (irq0). ? indirect hsync input detection check for the occurrence of a timer m1 capture/overflow interrupt (irq2). ? indirect csync input detection (sog) check for the occurrence of a timer m1 capture/overflow interrupt (irq2).
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 9 auto-detecting sync signal polarity the s3c8639/c863a/c8647 sync processor lets you detect automatically the polarity of vsync or hsync signals by hardware. to check h/vsync polarity, it uses 16 clocks of timer m2 (f osc /1000). you can detect the polarity of hsync signal inputted to hsync-i port through checking syncon1.0 by the 5-bit counter of sync processor. if syncon1.0 is ?1?, the polarity of the inputting hsync signal is positive. when syncon1.0 is ?0?, the polarity of hsync signal is negative. but when the inputted sync signal to hsync-i is composite sync signal (h+vsync signal), the staus of syncon1.0 may not be accurate. to detect the polarity of vsync signal, it uses syncon1.1. if syncon1.1 is ?1?, the polarity of vsync signal is positive. when the polarity of vsync signal is negative, syncon1.1 is ?0?. if vsync polarity is changing, syncon1.1 will be updated after a typical delay of 2ms, at 8 mhz f osc (1.33ms at 12 mhz f osc ). positive type negative type vsync frequency: max: 200 hz (5 ms) vsync pulse width: min: 10us max: 600 us figure 16-7. vsync input timing diagram
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 10 positive type negative type hsync frequency: max: 160 khz (6.25 us) hsync pulse width: min: 0.5 us max: 7.85 us figure 16-8. hsync input timing diagram
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 11 extracting v sync output when the vsync input at hsync-i or csync-i (p2.7) also contains hsync signals, you must extract the vsync component from the hsync (or csync) input. to do this, you use the 5-bit up/down counter. to extract the vsync component of the input signal, you first set the 5-bit up/down counter to operate in compare mode (syncon0.5 = ?1?). vsync output is enabled only when the minimum or maximum threshold value is reached. during vertical blanking, the counter decreases until it reaches a minimum value while the hsync-i or csync-i signal level is negative. or, the counter value increases until it reaches a maximum value while the hsync-i or csync-i signal level is positive (no overflow or borrow occurs). the timer m1 capture interrupt (irq2) can be enabled to verify that the vsync signal has been extracted successfully from the mixed input signal. composite sync (hsync-i input) 5-bit counter value 5-bit counter output figure 16-9. vsync extraction using an up/down counter
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 12 clamp signal output clamp signal output (clamp-o) must be synchronized with hsync output. the clamp-o signal can be transmitted to a vertically or horizontally driven integrated circuit to provide a pedestal level for image signals with programmable pulse width. the clamp signal is output on the ?front porch? of an hsync signal (no sog condition) or on the "back porch" of an csync signal (sog condition). you can control the polarity of clamp output signal with using syncon1.4. if you want to the negative pulse of clamp signal, you must set syncon1.4 to ?0?. if you set syncon1.4 to "1", the polarity of clamp output signal is positive. source hsync pedestal level front porch (no sog) back porch image signal clamp-o port output source hsync pedestal level front porch (no sog) back porch image signal clamp-o port output figure 16-10. clamp-o signal (sog and no sog condition)
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 13 differentiating sog from no sog the pulse width at the csync-i pin is different in sog and no sog conditions. in a sog condition, the pulse width at csync-i and hsync-i is identical. if a no sog condition exists, csync-i has a wider pulse width than hsync-i because the csync-i pulse is truncated at the base of the pedestal level (see figure 16-10). to differentiate the csync pulse, you must delay the csync-i pulse for about 150 ns and then compare its phase with that of the hsync -i pin signal. to indicate a sog condition, comparator logic for hsync and csync sets the syncon2.2 flag to ?1? whenever csync status differs from hsync status more than 32 times at the rising edge of hsync-i. to perform the comparison, first detect the polarity of the hsync-i signal. then configure the pin for positive output. (csync-i is always positive and requires no special settings.) to recognize the sog condition, you can poll the syncon2.2 status flag to detect when it is set to ?1?. csync port input 150 ns 150 ns hsync port input after 150 ns delay sog after 150 ns delay no sog figure 16-11. sync input at the hsync-i and csync-i pins hsync-o maximum delay is 250 ns clamp-o programmable clamping width (0, 250 ns, 500 ns, 1 us) figure 16-12. clamp-o signal delay timing
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 14 f f programming tip ? programming the sync processor this example shows how to program the sync processor to sample specifications. the sample program performs the following actions: ? confirm the presence of sync signal input ? detect the polarity of hsync or vsync signal input ;//************************************************************** ;//** title : definition flag ram for user (00h - 0fh) * ;//** * ;//** * ;//************************************************************** ; degausport equ 3 ;p0.3=degauss control pin(active h igh) suspndport equ 4 ;p0.4=suspend control pin(high) offport equ 5 ;p0.5=off control pin(low) muteport equ 7 ;p0.7=video mute control pin(low) ; selfrastport equ 0 ;p1.0=self-raster input pin s1 equ 1 ;p1.1=s-correction 1 s2 equ 2 ;p1.2=s-correction 1 ; ;x-ray equ 0 ;not used ;rotation equ 1 ;p2.1=pwm1 out (rotation) ;h-size equ 2 ;p2.2=pwm2 out (h-size) ;contrast equ 3 ;not used ;brightness equ 4 ;not used ;acl equ 5 ;p2.5=pwm5 out (acl) hsize_min equ 6 ;not used modelselport equ 7 ;p2. 7=model sel.input pin(14":l/15":h) ; pwrkeyport equ 0 ;p3.0=s/w power key input pin ledport equ 5 ;p3.5=led control scl equ 6 ;p3.6=scl(s/w iic.bus) sda equ 7 ;p3.7=sda ; ;fixed port. ;h_input equ 1 ;h-sync. input ;v_input equ 2 ;v-sync. input ;clamp equ 3 ;clamp output ;h_out equ 4 ;h-sync. output ;v_out equ 5 ;v-sync. output ;ddc_clock equ 6 ;ddc clock ;ddc_data equ 7 ;ddc data ; hsynciport equ 0 ;syncrd.0=hsynci pin vsynciport equ 1 ;syncrd.1=vsynci pin vsyncoport equ 3 ;syncrd.3=vsynco pin ; ;
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 15 // define flags ; ; syncp_fgr0 equ 00h ;sync-processor hsyncfin_fg equ 7 ;hsync signal counting every 10ms vsyncfin_fg equ 6 ;vsync signal find flag(vsync capture interrupt) vstblfreq_fg equ 5 ;stable vsync frequency input status hstblfreq_fg equ 4 ;stable hsync frequency input status normsync_fg equ 3 ;normal sync output mode(no pseudo sync signal) setsepsync_fg equ 2 ;indicate separate sync mode mixedsync_fg equ 1 ;mixed sync input period(composite sync input mode) ddchighspd_fg equ 0 ;ddc1 high speed mode(over 400hz) ; syncp_fgr1 equ 01h ; hpolarity_fg equ 7 ;hsync polarity => 1=positive, 0=negative vpolarity_fg equ 6 ;vsync polarity => 1=positive, 0=negative hnosync_fg equ 5 ;hsync freq. < 10khz vnosync_fg equ 4 ;vsync freq. < 40hz nosync_fg equ 3 ;no vsync & no hsync signal overhsync_fg equ 2 ;hsync over range : over 62khz overrange_fg equ 1 ;vsync over range : over 135hz ; mute_fgr equ 02h ; vmute_fg equ 7 ;being video mute chksyncstus_fg equ 6 ;video mute time end mutewaiting_fg equ 5 ;being video mute extension muterelse_fg equ 4 ;video mute release pwronwait_fg equ 3 ;power-on mute delay(2sec) psyncout_fg equ 2 ;pseudo sync output status normmwait_fg equ 1 ;count mute extension time(350ms) ; time_fgr equ 03h ; keydetect_fg equ 7 ;key detecting per 10ms degtime_fg equ 6 ;degaussing time(3sec) chkpwrkey_fg equ 5 ;checking power-key status per 10ms ; status_fgr equ 04h ; sfrasterin_fg equ 7 ;self-raster mode recall_fg equ 6 ;recall function(continuous key=3sec) userdel_fg equ 5 ;delete user data in eeprom(continuous key=5sec) findsyncsrc_fg equ 4 ; eeprom_fgr equ 05h ; userarea_fg equ 7 ;checking eeprom user data area closhsync_fg equ 6 ;searching closest hsync mode savedeep_fg equ 5 ;factory data saved eeprom ? eepdatard_fg equ 4 ;eeprom data read after mode changing nofactsave_fg equ 3 ;eeprom data read after mode changing ; tda9109_fgr equ 05h ; tdawrite_fg equ 2 ;write pwm data to tda9109 tdaread_fg equ 1 ;read from tda9109 ;
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 16 dpms_fgr equ 09h ; dpmsstart_fg equ 7 ;dpms mode start(3sec after abnormal sync signal) chkdpmscon_fg equ 6 ;dpms condition input(h<10khz,v<40hz) pwroffin_fg equ 5 ;power saving mode offmode_fg equ 4 ;off mode suspend_fg equ 3 ;suspend mode standby_fg equ 2 ;sta ndby mode ; iic_fgr equ 0ah ddccmd_fg equ 7 ;get ddc2b+ command lastbyte_fg equ 6 ;last tx data commfail_fg equ 5 ;communication fail(not ack) rewrite_fg equ 4 ;rewrite to eeprom reread_fg equ 4 ddc2mode_fg equ 3 reva0match_fg equ 2 ddc2btxmode_fg equ 1 ; checksum equ 0bh ;ddc2b+ bytecnt equ 0ch ;count number of tx data sendtype equ 0dh ;reply type numtxdbyte equ 0eh ;#(total tx byte -1) in master tx mode xxcntr equ 0fh ;number of rx data ; ; ;//***************************************************************** ;//** title : definition general purpose ram (10h - bfh) * ;//** * ;//** * ;//***************************************************************** ; tb1msr equ 10h ;1ms interval register(basic time reg.) tb10msr equ 11h ;10ms(count hsync event signal) tb100msr equ 12h ;100ms(func valid time => 7sec) dly1msr equ 13h ;1ms(cehcking writecycle time => 10ms) m10msr equ 14h ;10ms(checking mute time => sec, 350ms) s100msr equ 15h ;100ms(saving start time => 2sec) dg100msr equ 16h ;100ms(degaussing time => 3sec) dpms100msr equ 17h ;check dpms start(after no sync : 3sec) chksrastime equ 18h ;check self-raster input(maintain 70ms ?) ; hcount equ 20h ;double byte(even address + odd address) ; equ 21h hfreqstcnt equ 22h freqspcnt equ 23h averagehf equ 24h hfhighnew equ 25h ;current value of hsync freq high byte hflownew equ 26h hfhighdata equ 27h ; saved value of hsync freq high byte hflowdata equ 28h ;real hsync frequency = low nibble of hfreq high data + ;hfreq low data
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 17 ;ex> if, hfhighdata=#x2h, ;hflowdata=#58h => hsync frequency = 258h=60.0khz vcount equ 30h ;total number of timer0 counter within vsync period ; equ 31h ;double byte novtime equ 32h ;checking the sustaining time of no vsync signal ;if novtime > 30ms(under 33hz) => mute vfreqchigh equ 33h ;temp storage of timer0(vsync) overflow count t0ovfcntr equ 34h ;no vsync-int. service if ddc1 high freq. mode vfcurrnew equ 35h ;current vsync freq vfreqdata equ 36h ;saved vsync freq. vclkcntr equ 37h ;for auto recovery of ddc mode (ddc2b -> ddc1) ; polacntr equ 38h ;count number of polarity checking vpolacntr equ 39h ;increment when positive polarity ; umodeno equ 40h ;matched number of user mode fmodeno equ 41h ;factory mode readdata e qu 42h ;readed data from eeprom ; ep_bplus equ 50h ;eeprom & ram data ep_contrast equ 51h ;ka2504 ep_rgain equ 52h ep_ggain equ 53h ep_bgain equ 54h ep_coffbright equ 55h ;ka2504 ep_rcutoff equ 56h ep_gcutoff equ 57h ep_bcutoff equ 58h ep_acl equ 59h ;pwm5 ; ; edidaddr equ 80h ;page1 ram register ;edid address(00~7fh:128-byte) ; ;// working registers -> genernal ram ; ;r14 equ eepsubaddr ;sub address of eeprom/tda9109 ;r15 equ eepwrdata ;data to write in eeprom/tda9109 ;---> ka2504 pre -amp control ;r14 equ preampsubaddr ;sub address ;r15 equ preampctrldata ;data address ; ;// buffer for ddc2b+ protocol ; mbusbuff equ 0b0h ;for ddc2b+(00h-0bfh:16-byte) abusdstaddr equ 0b0h abussrcaddr equ 0b1h abusplength equ 0b2h abuscommand equ 0b3h ; : : ; equ 0bfh ;
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 18 ;############################################################## ; ;// ddc edid area : 00h - 7fh (128-byte : page 1) ; ;############################################################## ; ;//************************************************************** ;//** title : define control register's flags ;//** ;//** ;//************************************************************** ;// iic.bus control register ;// dcon bufen equ 3 ;tx/rx pre-buffer data register enable(0:normal, ;1: pre-buffer mode) ddc1mat equ 2 ;ddc address match(0:not match, 1:match) ddc1en equ 1 ;ddc1 tx mode enable sclf equ 0 ;scl falling edge detectio n ; ;// dccr(ddc clock control reg) dtxacken equ 7 dclksel equ 6 dinten equ 5 dpnd equ 4 ccr3 equ 3 ccr2 equ 2 ccr1 equ 1 ccr0 equ 0 ; ;// dcsr0(ddc control/status reg0) dmtx equ 7 dstx equ 6 dbb equ 5 ddcen equ 4 dal equ 3 daddmat equ 2 ;equ 1 ;not used for the ks88c6332/48/p6348 drxack equ 0 ; ;// dcsr1(ddc control/status reg1) stcondet equ 2 ;iic-bus stop condition detect dbufemt equ 1 ;data buffer empty status ;(0:write to tbdr, 1:tbdr -> ddsr) when tx dbufful equ 0 ;data buffer full status ;(0:read from rbdr, 1:ddsr -> rdbr) when rx ; ;tbdr ;transmit pre-buffer data register ;rbdr ;receive pre-buffer data register ;ddsr ;ddc data shift register ; ;// sync-processor control register ;// syncon0 sis equ 7 ;sync input selection(0:hsync, 1:csync)
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 19 hblken equ 6 ;hsync blanking enable(0:bypass, 1:blanki ng) voss equ 5 ;vsynco source selection(0:vsynci, 1:5-bit compare out) ; ;// syncon1 clmp1 equ 7 ; clmp0 equ 6 ;clampo pulse width fbps equ 5 ;front/back porch selection(0:back, 1:front) clmps equ 4 ;clampo polarity control(0:negative, 1:positive) vos equ 3 ;vsynco polarity control(0:by-pass, 1:invert) hos equ 2 ;hsynco polarity control(0:by-pass, 1:invert) vpol equ 1 ;vsync polarity detection(0:negative, 1:positive) ;read only hpol equ 0 ;hsync polarity detection(0:negative, 1:positive) ;r ead only ; ;// syncon2 unmixhsync equ 7 ;unmixed hsync detection ;(0:mixed sync, 1:unmixed sync), read only ccss equ 5 ;5-bit counter clock selection(0:fosc/2, 1:fosc/3) psgen equ 4 ;pseudo sync generation disable synod equ 3 ;sync signal output diasble sogi equ 2 ;sog check up5bsdet equ 1 ;5-bit up/down counter status changing det. vddls equ 0 ;vdd level selection(0:vdd=5v,1:vdd=3v) ; ;// watch-dog(basic) timer btclr equ 1 ; ;// timer m0 t0edgsel equ 4 ;timer m0 capture mode selection t0clr eq u 3 ;counter clear t0ovint equ 2 ;overflow interrupt enable t0int equ 1 ;capture enable t0capsel equ 0 ;capture input selection ;(0:external pin, 1:vsync from sync-processor) ; ;// timer m1 t1capsel equ 7 ;capture signal source selection ;(0:timer2, 1:vsynco from p) vedgsel equ 6 ;vsynco capture edge selection(0:rising, 1:falling) t1capen equ 5 ;capture interrupt enable t1pnd equ 4 ;capture interrupt pending flag t1clr equ 3 ;counter clear t1ovfint equ 2 ;overflow interrupt enable ; ;// timer m2 t2int equ 2 capintv1 equ 1 capintv0 equ 0 ; ; ; ;
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 20 ;// pre-amp sub-address mapping ;slave address=dch ; psuba_cont equ 00h ;contrast control psuba_sbnbr equ 01h ;bit7=soft blanking(1:on, 0:off) ;bit6-5=cut-off control offset current switch ;(cs2:160ua, cs1:80ua) ;bit4-0=brightness control psuba_rgain equ 02h ;r gain control psuba_ggain equ 03h ;g gain control psuba_bgain equ 04h ;b gain control psuba_cobr equ 05h ;cut-off brightness control psuba_rco equ 06h ;r cut-off control psuba_gco equ 07h ;g cut-off control psuba_bco equ 08h ;b cut-off control psuba_sw equ 0ah ;blanking on-off control ; ;// eeprom address mapping ; epa_cobr equ 0f6h ;ka2504 cut-off brightness epa_cont equ 0f7h ;ka2504 cut-off contrast epa_rgain equ 0f8h ;ka2504 r-gain epa_ggain equ 0f9h epa_bgain equ 0fah epa_rco equ 0fbh ;ka2504 r-cut off epa_gco equ 0fch epa_bco equ 0fdh epa_acl equ 0feh ; ; ; ;------------------------------------------------------------------ ;----- ddc2ab comunication command code ------ ;------------------------------------------------------------------ i_reset equ 0f0h i_idreq equ 0f1h ; i_asgnadr equ 0f2h i_capreq equ 0f3h i_applrprt equ 0f5h ; i_attention equ 0e0h i_idreply equ 0e1h i_capreply equ 0e3h ; i_getvcp equ 01h i_vcpfreply equ 02h i_setvcp equ 03h i_gettiming equ 07h i_resetvcpf equ 09h i_disablevcpf equ 0ah i_enablevcpf equ 0bh
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 21 savecurrset equ 58h i_timingreport equ 4eh ; i_getedid equ 54h saveedid equ 69h ; deluser equ 50h allmodesve equ 52 h ; savecolorset equ 7dh brtcontmax equ 0d2h ; ; ;//************************************************************* ;//** title : interrupt vector table * ;//** * ;//************************************************************* ; org 00e0h vector tm0ovf_int ;timer m0 overflow int.(irq0) vector vsyncdet_int ;timer m0 capture int.(irq0) vector tm2intv_int ;timer m2 interval int.(irq2) ; org 00e8h vector tm1cap_int ;timer m1 capture int.(irq1) ; org 00eah vector ddcnfa_int ;ddc iic-bus tx/rx int.(irq3) ; ;________________________________________________________________ ; org 0100h ;________________________________________________________________ ;//************************************************************** ;//** title : main program start from here * ;//** * ;//************************************************************** ; ;//************************************************************** ;//** title : << system reg. files initialization >> * ;//** * ;//** * ;//************************************************************** ; reset: di ;disable interrupt clr pp ;source, destination = page0 clr sym ;disable fast interrupt ld spl,#0ffh ;stack pointer srp #0c0h ;working reg. area ld imr,#00001111b ;timer m0,m1,m2, & ddc int. ;bit7 -> not used ;bit6 -> not used ;bit5 -> not used
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 22 ;bit4 -> not used ;bit3 -> irq3 ddc int. ;bit2 -> irq2 timer m1 cap. int. ;bit1 -> irq1 timer m2 int. ;bit0 -> irq0 timer m0 cap. & ovf . int. sb0 ;select bank 0 clr emt ;0 wait, internal stack area ld ipr,#00010001b ;group priority(int) undefined(a>b>c) ;tm2/tm1 > tm0 > ddc ld clkcon,#18h ;cpu=fx(no division) ld btcon,#0a2h ;watchdog timer disable ld wdtcon,#00h ;watchdog time = tbtovf ld stopcon,#5ah ;stop function disable ;initialize sync-processor control register ; ld syncon2,#10100000b ;b it7=read only ld syncon1,#11000000b ;clampo=negative polarity ;vsynco=5-bit counter compare output ld syncon0,#00100000b ;automatic hsync blanking, ;synco source=vsynci port ld phgen,#83 ;pseudo hsync = 48.19khz ld pvgen,#101 ;pseudo vsync = 59.64khz ; ;initialize timer control register ; ld tm0con,#10001111b ;timer0 clock source=@8mhz/8=1mhz(1us) ;capture rising mode ;enable capture/overflow interrupt ;capture source=vsync output path ;from sync-processor ld tm 1con,#00001100b ;source=hsynci ;capture disable ;capture source=timer2 interval time*10(10ms) ;enable capture interrupt ld tm2con,#00111101b ;timer2 interval=@8mhz/(8*1000)=1ms ; ;***************************************************************************** main: call chkddc2bi call chkddcrecover call chkhvpres ;check h/vsync presence call chkhvpol ;check h/vsync polarity ; ; jr main ;***************************************************************************** ; ;****************************************************** ;******* ddc2bi service routine ******* ;****************************************************** chkddc2bi tm iic_fgr,#01< s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 23 tm dcsr0,#01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 24 ; checkhv_range call chkhnosyncrange jp c,syncoffstate ;under 10khz ? ; chkhsyncdata call uhsyncchk ;check changing rate of hsync frequency jp c,syncoffstate ;if changing rate > 00hz call upolachk ;check polarity data jp c,syncoffstate ; chkpresnvsync cp novtime,#25 ;if novtime > 25ms(under 40hz) => mute jp ugt,chkvsyncsrc tm syncp_fgr0,#01< s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 25 jr z,chkmutetime chkhvprtn ret ; chkmutetime tm mute_fgr,#01< 35 0ms delay ; -> mute release clr m10msr ret ; muterelease and mute_fgr,#0ffh-(01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 26 ret syncoffstate: tm status_fgr,#01< separate ->composite ; ; ;//************************************************************************** ;//** title : s-correction ; ; hsync freq. < 35khz => s1=l, s2=l ; (r5=xxkhz) < 40khz => s1=l, s2=h ; < 49khz => s1=h, s2=l ; < 60khz => s1=h, s2=h ;//************************************************************************** ; h_countload ld r4,hfhighdata and r4,#00000011b ld r5,hf lowdata
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 27 div rr4,#10 ret s_correct call h_countload cp r5,#35 ;under 35khz ; ; ret ; ;//***************************************************************************************** ;//** title : adjust horizontal duty cycle(tda9109) ; ; hsync freq. < 35khz => 00h(tda9109 address)=48h ; < 41khz => 00h=49h ; < 46khz => 00h=4ah ; < 52khz => 00h=4bh ; < 56khz => 00h= 4ch ;//**************************************************************************************** ; updatehduty call h_countload cp r5,#35 ;under 35khz ; ; ret ; ;//************************************************************************ ;//** title : adjust mode size(pwm6, 14/15") ;15" h_sync freq. < 41khz => pwm6=#1bh ; (r5=xxkhz) < 46khz => pwm6=#4ah ; < 50khz => pwm6=#50h ; < 56khz => pwm6=#91h ; < 62khz => pwm6=#cdh ;//************************************************************************ ; adjmodesize call h_countload cp r5,#41 ;under 41khz ; ; ret ; ;//******************************************************************* ;//** title : adjust b_plus output ;//******************************************************************* ; b_plusout ld r6,ep_bplus ;ep_bplus=ka2511 b+ referance data call h_countload ; c p r5,#41 ;under 41khz ; ; add r6,#0 ;51khz - 55.9khz modebplusout ld r14,#0bh ;b+ sub-address ld r15,r6 ;b+ data or tda9109_fgr,#01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 28 call writecycle ret ;//********************************************************************************************* ;//** title : check mode change and h/v frequency range for mode detection ;//** normal fh <= 500hz ;//** normal fv <= 1hz ;//** if there is in the sync range , set carry ;//** hfhighnew --> bit7---> h-polarity ;//** bit6---> v-polarity ;//** ;//** inputs: r0,r1 ;//** outputs: ;//** preserves: ;//** corrupts: ;//********************************************************************************************* ; ;//*************************************************************************** ;//** title : check new polarity and old polarity ;//** ;//*************************************************************************** ; upolachk tm syncp_fgr0,#01< s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 29 ret ; ;//*************************************************************************** ;//** title : compare vertical frequency ;//** ;//** ;//*************************************************************************** uvsyncchk: ld r0,vfcurrnew cp r0,vfreqdata jr ult,revvsub sub r0,vfreqdata ; cmpfvrng cp r0,#1 ;compare 1hz jr ugt,updatevfdata or syncp_fgr0,#01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 30 stblhsyncin or syncp_fgr0,#01< s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 31 jr c,finivfcal add r0,#1 ;r0=xxhz(frequency=1/time) jr c,novsyncsignal ;overflow(over 256hz) ? jr contisub finivfcal ld vfcurrnew,r0 ret ; novsyncsignal clr vfcurrnew ;vfcurrnew <- 00hz ret ; ;//*************************************************************************** ;//** title : check h/v sync range ;//** 27khz(10eh) < fh < 62khz(15" 26ch) ;//** 40hz(28h) < fv < 135hz(87h) ;//** ;//** ;//** inputs: ;//** outputs: ;//** preserves: ;//** corrupts: ;//*************************************************************************** chkhvrange: ld r2,hfhighnew ld r3,hflownew rcf sub r3,#0eh ;#10eh=27khz sbc r2,#01 jr c,overhfrange ld r2,hfhighnew ld r3,hflownew rcf su b r3,#6ch ;#26ch=62khz sbc r2,#02 jr nc,overhfrange and syncp_fgr1,#0ffh-(01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 32 preamprelese call ctrlpreamp ;control pre-amp call initialkb2511 ;tda9109(initializing) g clr m10msr ; call videomute ;set power on condition ; clrdpmsflags clr dpms100msr ;clear dpms checking counter and dpms_fgr,#00000011b ;clear dpms flags tm status_fgr,#01< s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 33 ; ; ;//*************************************************************************** ;//** title : check h/v polarity for every 5ms ;//** ;//** ;//** inputs: vsynci port data, syncon1.0 ;//** outputs: hpolarity_fg/vpolarity_fg (in syncp_fgr1) ;//** preserves: ;//** corrupts: ;//*************************************************************************** ; chkhvpol: tm syncon0,#01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 34 ;//** corrupts: ;//*************************************************************************** tm0ovf_int: push pp ;256us interval interrupt clr pp inc vfreqchigh ;overflow counter for vsync freq. calculation inc t0ovfcntr pop pp ir et ; ;//************************************************************************************************** ;//** title : timer 1 capture interrupt(t1data=number of hsync signal for 10ms) ;//** ;//** ;//** inputs: hsync signal(event counter source) ;//** outputs: number of hsync signal for 10ms(separate sync input mode) ;//** preserves: ;//** corrupts: ;//************************************************************************************************** ; tm1cap_int: sb0 push pp clr pp and tm1 con,#0ffh-(01< s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 35 compsynccalcu ld hfreqstcnt,hfreqspcnt ld hfreqspcnt,tm1cntl tm syncon2,#01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 36 setmutechktime and mute_fgr,#0ffh-(01< s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 37 jr ugt,vsyncdetsrv clr t0ovfcntr or syncp_fgr0,#01< 00f8h for irq1 ;//** ;//** inputs: pc/control jig -> monitor (ddc1/2b/2b+) ;//** outputs: monitor -> pc/control jig (ddc1/2b/2b+) ;//** preserves: ;//** corrupts: ;//*************************************************************************** ; ddcnfa_int: sb1 push pp clr pp ; ;------------------------------------------------------------- ;---- ddc1 tx protocol processor ----- ;------------------------------------------------------------- tm dcon,#01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 38 clr tbdr ;first edid(#00h) clr edidaddr and dcon,#0ffh-(01< normal iic-bus and dccr,#0ffh-(01< pc) jp nz,master tm dcsr0,#01< pc) jr nz,chkddc2mode tm dcon,#01< monitor add r0,rxxcntr ld @r0,rbdr ;@(#mbusbuff+rxxcntr) <- rbdr(=rx buffer) inc rxxcntr pop r0 clr vclkcntr ;ddc error checking timer and dcon,#0ffh-(01< normal iic-bus interface mode ddcsrvrtn and dccr,#0ffh-(01< 00h -> p & s -> a1h -> .. jr ne,edidtx ld pp,#11h ;in this case : a0h -> 00h -> s -> a1h -> inc edidaddr ;edidaddr : 00h -> 01h (repeat start case)
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 39 ; edidtx ld pp,#11h cp edidaddr,#7fh ;edid=00h~7fh(page1) jr ule,prepnextaddr clr edidaddr ;first data prepnextaddr ld tbdr,@edidaddr ;tbdr=tx buffer tm dcsr1,#01< ddc2b mode ddc2bmode clr vclkcntr ;for ddc1 recovery mod e or iic_fgr,#01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 40 and iic_fgr,#0ffh-(01< pc(control jig)) pop r6 pop r5 pop r4 pop r3
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 41 pop r2 pop r0 di pop imr pop pp and dccr,#0ffh-(01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 42 ;db v_contrast ;$12 ;13 ;db v_rgain ;16h ;14 ;db v_ggain ;18h ;15 ;db v_bgain ;1ah ;16 ;db v_coffbright ;10h ;17 ;db v_rcoff ;6ch ;18 ;db v_gcoff ;6eh ;19 ;db v_bcoff ;70h ;20 ;db v_acl ;f6h ;21 ;db v_degauss ;01h ;22 ; ; ;******************************************************************** ;***** pre_amp data transfer format ****** ;***** ****** ;***** iic_p_amp_start ****** ;***** slave address :#0dch * ***** ;***** sub address :rgb_drv_tbl ****** ;***** data :@dataaddr ****** ;***** iic_p_amp_stop ****** ;******************************************************************** ; preamp_rgb_drv: push r0 push r1 push r2 ; sb0 clr r2 preamp_one_drv call iicbus_start ld r0,#0dch ;ka5204 slave address(#0dch) call p_amp_drv_byte tm iic_fgr,#01< s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 43 ; ; rgb_drv_tbl db 00h ;pre_amp (contrast) db 01h ;pre_amp (brightness) db 02h ;pre_amp (r_gain) db 03h ;pre_amp (g_gain) db 04h ;pre_amp (b_gain) db 05h ;pre_amp (osd contrast) db 07h ;pre_amp (r_cutoff) db 08h ;pre_amp (g_cutoff) db 09h ;pre_amp (b_cutoff) db 0ah ;switch ; ; ;********************************************************************* ;****** preamp display initidal ******* ;****** mfr. : samsung electronc ******* ;****** type : ka2504 ******* ;********************************************************************* ;****** preamp start condition ******* ;********************************************************************* iicbus_start or btcon,#01<< btclr ;clear watch-dog timer or p3,#11000000b ;p3.7/6 <- high(sda,scl) call delaynop ;iic-start and p3,#0ffh-(01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 44 ret ; ;------------------------------------------------------------------------------- ;------ shift left one byte -------- ;------ parameter : r10 : shift data -------- ;------ r11 : bit counter -------- ;------------------------------------------------------------------------------- p_amp_drv_byte ld r1,#8 shiftleft rlc r0 jr nc,data_low or p3,#01< s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 45 ld ep_contrast,#0ffh ld ep_rgain,#3fh ld ep_ggain,#39h ld ep_bgain,#32h ld ep_rcutoff,#8ah ld ep_gcutoff,#80h ld ep_bcutoff,#0a6h ld ep_acl,#76h jr ctrlka2504 ; ldeeprgb ld r14,#epa_cobr ;brightness data call readeepdata ld ep_coffbright,readdata inc r14 ;contrast data call readeepdata ld ep_contrast,readdata inc r14 ;r-gain call readeepdata ld ep_rgain,readdata inc r14 ;g-gain call readeepdata ld ep_ggain,readdata inc r14 ;b-gain call readeepdata ld ep_bgain,readdata inc r14 ;r-cutoff call readeepdata ld ep_rcutoff,readdata inc r14 ;g-cutoff call readeepdata ld ep_gcutoff,readdata inc r14 ;b-cutoff call readeepdata ld ep_bcutoff,readdata ; ld r14,#epa_acl ;acl data call readeepdata ld ep_acl,readdata ; ctrlka2504 ld r14,#psuba_sbnbr ;brightness & soft blanking ld r15,#80h call preamp_rgb_drv sb1 ld pwm5,ep_acl ;acl sb0 ; repeatpreamp ld r14,#psuba_cont ld r 15,ep_contrast call preamp_rgb_drv ld r14,#psuba_cobr ld r15,ep_coffbright call preamp_rgb_drv ;
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 46 ld r14,#psuba_rgain ;ka2504 sub address ld r15,ep_rgain ;dataaddr call preamp_rgb_drv ld r14,#psuba_ggain ld r15,ep_ggain call preamp_rgb_drv ld r14,#psuba_bgain ld r15,ep_bgain call preamp_rgb_drv ld r14,#psuba_rco ld r15,ep_rcutoff call preamp_rgb_drv ld r14,#psuba_gco ld r15,ep_gcutoff call preamp_rgb_drv ld r14,#psuba_bco ld r15,ep_bcutoff call pr eamp_rgb_drv ret ; ;-------------------------------------------------------------------------------------- ;-------- initialize iic.bus control register ----------- ;-------------------------------------------------------------------------------------- iniddcmodule sb1 ld dccr,#10100100b ;enable tx ack signal ;enable iic.bus tx/rx int. ;include ddc1 tx int. ;100khz clock speed clr dcsr0 ld dar0,#0a0h ;#0a0h=monitor address(ddc2b) ld dar1,#6eh ;#6eh=m onitor address(ddc2b+/2bi) ld dcsr0,#00010000b ;dcsr.7/6=master/slave mode ;dcsr.5=start/stop(when write), ;busy signal status(read) ;dcsr.4=enable ddc module ;dcsr.3=arbitration procedure status ;dcsr.2=address-as-slave status ;dcsr.1=general call ;dcsr.0=ack bit status clr tbdr ;first edid data ld pp,#11h inc edidaddr clr pp sb0 ret ; ;******************************************************************** ;****** read 1byte in eeprom ****** ;****** by s/w iic.bus interface ****** ;******************************************************************** ; read1byte: push r0 push r1
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 47 push r2 call iicbus_start ;iic.bus protocol start tm tda9109_fgr,#01< slave -> s -> #a1h -> read clr r2 jr shiftstart ; ldtdaslave ld r0,#8dh ;#8c/8dh=tda9109 salve address ld r2,#2 and td a9109_fgr,#0ffh-(01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 48 setcf scf datarotate rlc r0 and p3,#0ffh-(01< s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 49 cp r5,r6 jr eq,rddatartn tm iic_fgr,#01< sub -> data clr r2 jr writestart ; writetda ld r0,#8ch ;#8ch=tda9109 salve address ; clr r2 writestart ld r1,#8 txdatashift rlc r0 jr c,txdata1 and p3,#0ffh-(01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 50 nextbwrite or p3conh,#11000000b ;sda(p3.7)=output and p3,#0ffh-(01<word->d1>d2->d3->d4->stop ld r2,#6 ;word addr -> d1 -> d2 -> d3 -> d4 nexttx1byte ld r1,#8 txndatashift rlc r0 jr c,txndata1 and p3,#0ffh-(01< s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 51 or p3conh,#11000000b ;sda(p3.7)=output and p3,#0ffh-(01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 52 or p3,#01< ddcdump: ld pp,#11h ldw rr2,#ddcdata ld r4,#00h ;r4=address(00h-7fh:128-byte)
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 53 writeedid ldci r5,@rr2 ;r5=data ld @r4,r5 inc r4 cp r4,#80h jr ult,writeedid clr pp ret ;------ ----------------- ddcdata db 00h,0ffh,0ffh,0ffh,0ffh,0ffh,0ffh,00h db 4ch,2dh,70h,4dh,00h,00h,00h,00h db 0ah,05h,01h,00h,2eh,1fh,17h,71h,0e8h,07h,65h,0a0h,57h,46h,9ah,26h db 10h,48h,4ch,0ffh,0feh,00h,01h,01h,01h,01h,01h,01,01h,01h,01h,01h db 01h,01h,01h,01h,01h,01h,68h,29h,00h,80h,51h,00,24h,40h,30h,90h db 33h,00h,32h,0e6h,10h,00h,00h,18h,01h,01h,01h,01h,01h,01h,01h,01h db 01h,01h,01h,01h,01h,01h,01h,01h,01h,01h,01h,01h,01h,01h,01h,01h db 01h,01h,01h,01h,01h,01h,01h,01h,01h,01h,01h,01 h,01h,01h,01h,01h db 01h,01h,01h,01h,01h,01h,01h,01h,01h,01h,01h,01h,01h,01h,00h,0bah ; ; ; < edid data > edidtoram: push r0 ;write edid(128-btye) to eeprom page0 push r1 push r2 push pp ld pp,#11h ld r4,#00h ;r4=ram address(50h-cfh:128-byte) ld r14,#00h ;r14=start address of edid ; call iicbus_start ;iic.bus protocol start ; ld r0,#0a0h ;sequential read operation clr r2 ; <= #a0h(page0) -> word -> s -> #a1h -> ead.... shift1byte ld r1,#8 ;1byte rotatedata rlc r0 ;rota te left sdadata(=r0) jp c,seqdata1 and p3,#0ffh-(01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 54 cp r2,#01 jr uge,restart ld r0,r14 ;sdadata <- r14 inc r2 ;sdacntr++ jr shift1byte ; restart call iicbus_start ld r0,#0a1h ;sdadata <- #0a1h inc r2 ;sdacntr++ jr shift1byte ; datarx and p3conh,#11110011b ;sda(p3.5)=input nop ld r1,#8 dataread or p3,#01< s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 55 call writecycle inc r14 cp r14,#0fh ;00-0fh ? jr ule,conti2511ini ret ; ;// kb2511 default data ;h_duty(40) / h posi(40) / free run(00) / hfocus(90) ;hfocuskey(10) / vramp(c0) / vposi(40) / s correct(20) ;c correct(20) / keystone(a0) / ew size(c0) / b plus(40) ;v moire(00) / side pin(a0) / parallel(a0) / vfocus(20) ; tdafruntbl db 4bh,40h,15h,9fh,14h,0c0h,40h,16h ;9109(0-7) db 32h,0a0h,0c0h,30h,00h,0a0h,0a0h,20h ;48khz free running ; ;//************************************************************************************ ;//********** the h/w iic read/write programming tip ************ ;//************************************************************************************ ; rxmode equ 6 ;iic receive mode flag rxack equ 0 ;acknowledgement check flag ; iic_fgr equ 10h ;iic status control check register commfail_fg equ 3 ;iic communication fail check flag eepromwri_fg equ 2 ;eeprom writing flag iicread_fg equ 1 ;iic reading flag rw_end_fg equ 0 ;iic read/write ending check flag ; rxtemp equ 20h ;temporary receiving data register txtemp equ 21h ;temporary transmitting data register iiccntr equ 22h ;iic read/write counter register sub_addr equ 23h ;slave device sub-address trans_data equ 80h ;transmitting data rx_data equ 90h ;receiving data ; ;//************************************************************************************ ;//********** < n-byte write program > ************ ;//************************************************************************************ ;//s(start) -> a0h -> subaddress -> n-bytedata -> p(stop) write_nbyte: ld sub_addr,#10h ;sub_addr = subaddress ld trans_data,#01h ;trans_data = tx data(8-byte) ld trans_data+1,#23h ld trans_data+2,#45h ld trans_data+3,#67h ld trans_data+4,#89h ld trans_data+5,#0abh ld trans_data+6,#0cdh ld trans_data+7,#0efh ld txtemp,#80h or iic_fgr,#01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 56 ; write_cycle: sb1 ;select bank 1 ld dcon,#08h ;enable prebuffer register ld dccr,#00100101b ;enable iic interrupt or dcsr0,#11010000b ;master tx mode & iic module enable ld tbdr,#0a0h ;#0a0h=slave device address or dcsr0,#00100000b ;iic start signal generation sb0 ;select bank 0 ; iic_write: tm iic_fgr,#01< s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 57 jr z,iicreadmode ; cp iiccntr,#9 ;iiccntr(2-9) = 8-byte write jr ult,conti_wri and dcsr0,#11011111b ;stop signal output clr iiccntr ;clear tx counter or iic_fgr,#01< 8-byte read jr ult,conti_read ; and dcsr0,#11011111b ;stop signal output clr iiccntr ;clear rx counter ld @rxtemp,rbdr ;@rxtemp = last rx data or iic_fgr,#01< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 58 and dcsr0,#11011111b ;stop signal output jr iic_rtn read_mode ld tbdr,#0a1h ;read mode slave address inc iiccntr ;change to read mode or dcsr0,#10000000b and dcsr0,#10111111b ;master receive mode or dcsr0,#00100000b ;iic restart signal output jr iic_rtn ; ;//************************************************************************************ ;//********** < n-byte read program > *********** ;//************************************************************************************ ;s(start) -> a0h -> sub address -> rs(restart) -> a1h -> n-byte read -> p(stop) read_1byte: ld sub_addr,#10h ;slave device subaddress ld rxtemp,#90h or iic_fgr,#01< s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 59 //#include "s3c863a.h" //#include "insam8.h" // type definition typedef unsigned char usch; typedef unsigned int usin; //********************* // macro definition // ******************** #define bittru(sfr,bit) (sfr & (1< sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 60 // ***************************** // control register definition // ***************************** // sync-processor part // syncon0 #define hiport 7 // hsync input selection (or csync-i) #define hblken 6 // enable hsync blanking #define udcntout 5 // vsynci port selection (or 5-bit compare output) // syncon1 #define clmp1 7 // clamp generation #define clmp0 6 #define bporch 5 // back porch clamp signal (or front porch) #define clmppol 4 // clamp signal polarity #define invtvpol 3 // invert vsync-o signal (or by-pass) #define invthpol 2 // i nvert hsync-o signal (or by-pass) #define posivpol 1 // positive vsync-i polarity (or negative) #define posihpol 0 // positive hsync-i polarity (or negative) // syncon2 #define unmixhperi 7 // unmixed hsync periods #define cnt5src 5 // 5-bit counter source #define dispseudo 4 // disable pseudo sync #define dissyncout 3 // inhibit sync signal output #define sogi 2 // sog detection #define compsync 1 // composite sync detection #define syncsrc 1 #define vdd3vsel 0 // when vdd=3v // ddc(iic) part // dcon (ddc control reg.) #define prebufen 3 // enable pre-buffer data register #define ddc1mat 2 // dar0 address match #define ddc1en 1 // enable ddc1 module #define sclf 0 // detect falling edge of scl line // dccr (ddc clock control reg.) #define dtxacken 7 // enable transmit acknowledge #define dclksel 6 // tx clock source selection #define enddcint 5 // enable ddc module interrupt #define ddcpnd 4 // ddc module interrupt pending // dcsr0 (ddc control/status reg.0) #define mst 7 // 1=master, 0=slave mode #define txd 6 // 1=transmit, 0=receive mode #define busstsp 5 // 1=bus busy or start signal #define enddc 4 // ddc module enable #define al 3 // arbitration lose #define datafld 2 // 1=data field, 0=address field #define nack 0 // not received acknowledge // dcsr1 (ddc control/status reg.1) #define stopdet 2 // stop condition detection #define bufemt 1 // data buffer empty #define bufful 0 // data buffer full
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 61 // timer part // btcon (watch-dog timer) #define wdclr 1 // clear basic timer counter // tm0con (timer0) #define capfall 4 // capture on falling mode #define t0clr 3 // clear timer0 counter #define t0ovfint 2 // enable timer0 overflow interrupt #define t0capint 1 // enable timer0 capture interrupt #define t0capvs 0 // capture source selection(1:vsync, 0:tm0cap) // tm1con (timer1) #define t1capvs 7 // capture source selection(1:vsync, 0:t2 interval) #define t1capfleg 6 // vsynco capture edge selection #define t1capint 5 // enable timer1 capture #define t1pnd 4 // timer1 pending bit #define t1clr 3 // clear timer1 counter #define t1ovfint 2 // enable timer1 overflow interrupt //tm2con (timer2) #define t2int 2 // enable timer2 interrupt /******************************************************************** definition of slave address ********************************************************************/ #define defl 0x8c //; deflection processor #define eep 0xa0 //; eeprom #define preamp 0xdc //; video amplifier #define osd 0xba //; osd processor // ***************************** // general registers definition // ***************************** // #define bit0 0 struct reg00 { usin keydetect : 1; usin mvaccel : 1; usin chkhfreq : 1; usin keyscan : 1; usin degaussing : 1; usin keyactive : 1; usin chksvtime : 1; } ; // time_fgr struct reg01 { usin pwronmute : 1; usin selfrasin : 1; usin recall : 1;
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 62 usin userdel : 1; usin powerdown : 1; usin overrange : 1; usin vsyncdet : 1; } ; // status_fgr struct reg02 { usin ddc2b : 1; usin ddccmd : 1; usin ddccitxd : 1; } ; // ddc_fgr struct reg03 { usin novsync : 1; usin nohsync : 1; usin nohvsync : 1; usin dpmsstart : 1; usin dpmscond : 1; } ; // dpms_fgr struct reg04 { usin dataread : 1; usin datasave : 1; usin usedeeprom : 1; usin nearhfreq : 1; usin endmodesrch : 1; usin nofactmode : 1; } ; // eeprom_fgr //************************************************* // code usch edid_tbl[0x80]= { 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00, 0x4c,0x2d,0x70,0x4d,0x00,0x00,0x00,0x00, 0x0a,0x05,0x01,0x00,0x2e,0x1f,0x17,0x71, 0xe8,0x07,0x65,0xa0,0x57,0x46,0x9a,0x26, 0x10,0x48,0x4c,0xff,0xfe,0x00,0x01,0x01, 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, 0x01,0x01,0x01,0x01,0x01,0x01,0x68,0x29, 0x00,0x80,0x51,0x00,0x24,0x40,0x30,0x90, 0x33,0x00,0x32,0xe6,0x10,0x00,0x00,0x18, 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, 0x01,0x01,0x01,0x01,0x01,0x01,0x00,0xba };
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 63 #include #include #include #define comp_range 10 // khz (tolerance of composite-sync) #define sep_range 5 // khz #define noh_range 10 // under 10khz #define hf_min 28 // normal hsync range=28khz-96khz #define hf_max 96 #define vf_min 40 // normal vsync range=40hz-160hz #define vf_max 160 usch delta_hf; // output to timer2 interrupt routine usin hfreq_save; // output usch vfreq_save; extern usin hf_new; // from timer1(sep-sync)/timer2(comp-sync) interrupt extern usin vcount; // from vsync interrupt extern usch novsynctime; // from vsync interrupt extern usch tdpms100ms; extern struct reg00 time_fgr; extern struct reg01 status_fgr; extern struct reg03 dpms_fgr; extern struct reg04 eeprom_fgr; static usin hf_old; static usch vf_new; static usch vf_old; static usch tmute10ms; static struct reg0 { usin stbvfreq : 1; usin stbhfreq : 1; usin ddchighspd : 1; usin : 3; // not used usin posihsync : 1; usin posivsync : 1; } syncp_fgr0, *psyncp_fgr0; static struct reg1 { usin scrnmute : 1; usin muterelse : 1; usin psyncout : 1; usin endmute : 1; usin normmute : 1; usin quitpsync : 1; } syncp_fgr1;
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 64 extern void selfraster_end(void); // 'main.c' extern void osd_off(void); // 'osd_drv.c' extern void deflect_ini(void); // 'initial.c' extern void ctrl_preamp(void); // 'initial.c' extern void timedelay_ms10(void); // 'initial.c' extern void write_swiic(usch, usch, usch); // 'swiic.c' usch chk_hnosync_range(void); usch chk_hf_change(void); usch chk_pol_change(void); usch chk_vf_change(void); usch chk_hv_range(void); void pseudosync_gen(void); void chng_vsync_src_sep(void); void chng_vsync_src_comp(void); void mute_release(void); void quit_psync_out(void); void s_correct(void); void h_lin_out(void); void update_hsync(usin hfnew); void stable_hsync(usin hfave); void pola_update(void); void set_posi_pola(void); void chkmutetime(void); // // strat sync-processor function void syncprocessor(void) { psyncp_fgr0 = &syncp_fgr0; // check hsync frequency & polarity if(chk_pol_change()) pseudosync_gen(); else if(time_fgr.chkhfreq==1) { // 10ms flag time_fgr.chkhfreq=0; chkmutetime(); if(chk_hnosync_range() || chk_hf_change()) pseudosync_gen(); // video mute } // check vsync source, frequency & status // vsync freq. is under 40hz if(novsynctime>25) { novsynctime=0; dpms_fgr.novsync=1; if(dpms_fgr.nohsync==1) dpms_fgr.nohvsync=1; if(bitfals(syncon2,compsync)) chng_vsync_src_sep(); // change vsync input source to vsync-i port else chng_vsync_src_comp(); // vsync-i port -> 5-bit u/d counter output pseudosync_gen();
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 65 } // vsync freq. is over 40hz else if(status_fgr.vsyncdet==1) { // vsync interrupt flag dpms_fgr.novsync=0; dpms_fgr.nohvsync=0; status_fgr.vsyncdet=0; if(bittru(syncon2,sogi)) { bitset(syncon1,bporch); // back porch clamp signal bitclr(syncon0,hiport); // select csync port } // calculate vsync freq. if(vcount) // 'vcount' is a interval time // vcount(time)= 2us * num. of timer1 counter vf_new=500000/vcount; // freq=1/time if(chk_vf_change() || chk_hv_range()) pseudosync_gen(); // change rate of vfreq > 1hz, or over frequency range // normal h/vsync signal input // test condition of video-mute release else if(syncp_fgr1.muterelse==1) ; // after video-mute has been released // video-mute processing routine else if(syncp_fgr1.endmute==1) // 'endmute' flag is set after 'quit_psync_out()' // and if mute-delay time is passed. mute_release(); else if(syncp_fgr0.stbhfreq==1 && syncp_fgr0.stbvfreq==1) quit_psync_out(); // output : pseudo-sync -> input sync-signal } } // ******************************* // this function is executed when // 1. mode change // 2. no/over sync input // 3. polarity change // ******************************* void pseudosync_gen(void) { if(status_fgr.selfrasin==0 // self-raster mode or already mute processing ? && syncp_fgr1.psyncout==0){ bitclr(p0,muteport); // active low bitset(syncon1,posivpol); // pseudo-vsync polarity is positive bitset(syncon1,posihpol); bitclr(syncon2,dispseudo); // pseudo-sync gen. bitset(p3,cs1); // control s-correction cap.(free run=48khz) : osd_off(); // osd window off
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 66 syncp_fgr1.scrnmute=1; syncp_fgr1.psyncout=1; syncp_fgr1.quitpsync=0; syncp_fgr1.muterelse=0; syncp_fgr1.endmute=0; syncp_fgr0.stbvfreq=0; syncp_fgr0.stbhfreq=0; eeprom_fgr.datasave=0; time_fgr.chksvtime=0; } } // change vsync input source : vsync-i port <-> 5-bit up/down counter output // void chng_vsync_src_sep(void) { bitclr(syncon0,udcntout); // change vsync input source to vsync-i port bitclr(syncon0,hblken); // disable hsync blanking bitset(tm1con,t1capint); // enable timer1 capture mode } void chng_vsync_src_comp(void) { bitset(syncon0,udcntout); // input source: vsync-i -> 5-bit u/d counter output bitclr(tm1con,t1capint); // disable t1 capture interrupt // change calculation method of hsync frequency // => 10ms interval -> sum(each 1ms counter by 10) bitclr(syncon2,compsync); // clear latch status of 5-bit u/d couner bitclr(syncon2,sogi); // clear sog detection counter } // after stable sync signal input // void quit_psync_out(void) { pola_update(); set_posi_pola(); // setting positive polarity for h/vsync-o if(syncp_fgr1.quitpsync==0) { bitset(syncon2,dispseudo); // quit pseudo-sync gen. syncp_fgr1.psyncout=0; syncp_fgr1.quitpsync=1; s_correct(); h_lin_out(); eeprom_fgr.dataread=1; // loading pwm data from eeprom in 'eeprom_rdwr.c' if(status_fgr.pwronmute==1) { // power-on muting time:2sec syncp_fgr1.normmute=1; // load data -> 300ms delay -> mute release tmute10ms=0; } } }
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 67 // after stable sync signal input & video-mute waiting & dac output void mute_release(void) { syncp_fgr1.scrnmute=0; //syncp_fgr1.endmute=0; syncp_fgr1.muterelse=1; bitset(p0,muteport); // release mute-port(p0.0) } usch hfkhz_load(usin hfreq) { usin hfreq_khz; hfreq_khz=hfreq; hfreq_khz &= 0x03ff; // hsync range is under 100khz hfreq_khz /= 10; return hfreq_khz; } // ******************************* // checking the condition of no hsync signal // ******************************* usch chk_hnosync_range(void) { usch hf_khz; hf_khz=hfkhz_load(hf_new); if(hf_khz < noh_range) { // under 10khz dpms_fgr.nohsync=1; return 1; } else { dpms_fgr.nohsync=0; dpms_fgr.nohvsync=0; return 0; } } // ***************************************** // check changing rate of hsync frequency // tolerance of stable hsync signal // is under 500hz(seperate-sync) // ***************************************** usch chk_hf_change(void) { usin hfreq, hf_ave, temp; hf_ave=(hf_new+hf_old)/2; hf_old=hf_new; delta_hf=hf_ave/10; // khz _di(); temp=hfreq_save&0x03ff;
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 68 hfreq=(temp>=hf_new)? (temp-hf_new):(hf_new-temp) _ei(); // always positve value if((bittru(syncon0,udcntout) && (hfreq>comp_range)) { update_hsync(hfreq); // update freq. of hsync input signal return 1; } else if((bitflas(syncon0,udcntout) && (hfreq>sep_range)) { update_hsync(hfreq); return 1; } else stable_hsync(hf_ave); // stable state of hsync input return 0; } } // void update_hsync(usin hfnew) { syncp_fgr0.stbhfreq=0; hfreq_save &= 0xc000; // bit 15,14=polarity hfreq_save |= hfnew; } // void stable_hsync(usin hfave) { syncp_fgr0.stbhfreq=1; hfreq_save &= 0xc000; hfreq_save |= hfave; } // ********************************************** // check changing rate of vsync frequency // tolerance of stable vsync signal is under 1hz // ********************************************** usch chk_vf_change(void) { usch temp; vf_old=vf_new; vfreq_save=vf_new; temp=(vf_old>=vf_new)? (vf_old-vf_new):(vf_new-vf_old); if(temp>1) { // temp=|vf_old-vf_new| syncp_fgr0.stbvfreq=0; return 1; } else { // stable vsync signal syncp_fgr0.stbvfreq=1; return 0; } }
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 69 // ******************************* // checking polarity change // ******************************* usch chk_pol_change(void) { if(syncp_fgr1.psyncout==0) { if(syncp_fgr0.posivsync != bittru(syncon1,posivpol)) { pola_update(); return 1; } else if(bitfals(syncon0,udcntout)) { // separate-sync if(syncp_fgr0.posihsync != bittru(syncon1,posihpol)) { pola_update(); return 1; } else { set_posi_pola(); return 0; } } } return 0; } // update polarity flags void pola_update(void) { usin hf_temp, pola_temp; if(bittru(syncon0,udcntout)) { // composite-sync if(bittru(syncon1,posivpol)) { syncp_fgr0.posivsync=1; syncp_fgr0.posihsync=1; } else { syncp_fgr0.posivsync=0; syncp_fgr0.posihsync=0; } } else { // seperate-sync if(bittru(syncon1,posivpol)) syncp_fgr0.posivsync=1; else syncp_fgr0.posivsync=0; if(bittru(syncon1,posihpol)) syncp_fgr0.posihsync=1; else syncp_fgr0.posihsync=0; } hf_temp=hf_new;
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 70 hf_temp &= 0x03ff; pola_temp=*(usin *)psyncp_fgr0; pola_temp <<= 8; pola_temp &= 0xc000; // masking except polarity flags hf_temp |= pola_temp; hfreq_save=hf_temp; // bit15/14=polarity, bit9~0=hsync frequency } void set_posi_pola(void) { if(syncp_fgr0.posivsync==1) bitclr(syncon1,invtvpol); // by-pass vsync signal else bitset(syncon1,invtvpol); // inverting vsync signal if(syncp_fgr0.posihsync==1) bitclr(syncon1,invthpol); else bitset(syncon1,invthpol); } // ******************************* // check range of the h/vsync signal // ******************************* usch chk_hv_range(void) { usch hf_khz; hf_khz=hfkhz_load(hf_new); // checking range of hsync/vsync signal if(hf_khzhf_max || vf_newvf_max) { status_fgr.overrange=1; return 1; } else { // normal h/vsync signal (28khz normal sync mode bitclr(p0,suspndport); // release suspand port(12v line) timedelay_ms10(); bitset(p0,offport); // release off port(5v line) write_swiic(defl,hduty,0); // h-duty off deflect_ini(); // free running ctrl_preamp(); tmute10ms=0; pseudosync_gen(); // video-mute status_fgr.pwronmute=0; // waiting time=2sec status_fgr.powerdown=0; } tdpms100ms=0;
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 71 dpms_fgr.dpmsstart=0; if(status_fgr.selfrasin==1) selfraster_end(); return 0; } } // control s-correction cap. void s_correction(void) { usch hf_khz; hf_khz=hfkhz_load(hfreq_save); if(hf_khz<33) { : } else if(hf_khz<36) { : } : } // control h-linearity with pwm6 void h_lin_out(void) { usch hf_khz; hf_khz=hfkhz_load(hfreq_save); if(hf_khz<=30) { : } : } // ******************************* // 10ms timer for video-mute // ******************************* void chkmutetime(void) { if(syncp_fgr1.normmute==1) { if(++tmute10ms>30) { // mute delay time=300ms syncp_fgr1.normmute=0; syncp_fgr1.endmute=1; } } else if(status_fgr.pwronmute==0) { if(++tmute10ms>200) { // mute delay time=2sec status_fgr.pwronmute=1; syncp_fgr1.endmute=1; } } }
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 72 #include #include #include usch novsynctime // to "syncproc.c" usin vcount; // to "syncproc.c" usch vclkcntr; // to "syncproc.c" usin hf_new; // to "syncproc.c" usch tbase10ms; usch tkeyact100ms; usch tdgaus100ms; usch tsave100ms; usch tdpms100ms; usch ddc_rxtxbuf[32]; // ddc comm. buffer. // 1'st byte = dest. address (2bi: 6eh(host to display), 6fh(dtoh)) // 2'nd byte = src. address (2bi: 51h(htod), 6eh(dtoh)) // 3'rd byte = length // 4'th byte = command extern usch delta_hf; // from "syncproc.c" extern usch wrcycletime; // from "swiic.c" extern usch *txdata; // from "ddc2bci.c" extern usch bytecnt; usch t0ovfcnt; extern struct reg00 time_fgr; extern struct reg01 status_fgr; extern struct reg02 ddc_fgr; extern struct reg03 dpms_fgr; extern struct reg04 eeprom_fgr; extern tinyp usch tinyp *edidaddr; ;ddc extern tinyp usch ddc_page1[0x80]; #define end_ddc 0x7f void ms10timer(void); void ddc2bi(void); // timer0 overflow interrupt (count vsync interval) // interrupt [t0ovf_int] void t0ovf_interrupt(void) { usch pp_copy; pp_copy=pp; // push pp pp=0;
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 73 t0ovfcnt++; pp=pp_copy; } // timer0 capture interrupt (capture vsync signal) // interrupt [vsync_int] void vsync_interrupt(void) { usch pp_copy; _sb0(); pp_copy=pp; pp=0; novsynctime=0; if(t0ovfcnt>10) { // under 195hz (256*2*10 us) ? status_fgr.vsyncdet=1; vcount=(tm0data+(t0ovfcnt*256)); t0ovfcnt=0; // increment vsync counter for ddc1 recovery _sb1(); if(ddc_fgr.ddc2b==0 && bitfals(dcon,ddc1en)) vclkcntr++; _sb0(); } else t0ovfcnt=0; pp=pp_copy; } // timer1 capture interrupt (event counter for hsync signal(seperate-sync)) // interrupt [t1cap_int] void t1cap_interrupt(void) { usin temp, pp_copy; _sb0(); pp_copy=pp; pp=0; bitclr(tm1con,t1pnd); // clear pending bit if(bittru(tm1con,t1capint)) { temp=(usin)tm1datah; temp <<= 8; temp += (usin)tm1datal; hf_new=temp; // hsync frequency for 10ms(timer2 interval * 10) delta_hf=0; } pp=pp_copy; }
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 74 // timer2 interval interrupt (1ms interval int. & calcu. hsync freq.(comp-sync)) // interrupt [t2intv_int] void t2intv_interrupt(void) { usin hf_cnt; usch pp_copy; static usch hf_startcnt; static usch hf_stopcnt; static usin hcount; static usch tbase1ms; static usch tbase10ms; _sb0(); pp_copy=pp; pp=0; if(bittru(syncon0,udcntout)) { hf_startcnt=hf_stopcnt; hf_stopcnt=tm1cntl; if(bitfals(syncon2,unmixhperi)) hcount += delta_hf; else { hf_cnt=hf_stopcnt-hf_startcnt; hcount += hf_cnt; } } if((++tbase1ms)>=10) { // over 10ms ? tbase1ms=0; time_fgr.chkhfreq=1; time_fgr.keyscan=1; ms10timer(); // set reletive reg. to time if(bittru(syncon0,udcntout)) hf_new=hcount; // hsync freq.(number of hsync event for 10ms) } novsynctime++; pp=pp_copy; } void ms10timer(void) { wrcycletime++; if(++tbase10ms>10) { tbase10ms=0; // check degaussing time if(time_fgr.degaussing==1 && !(--tdgaus100ms)) { bitclr(p3,degausport); time_fgr.degaussing=0; } if(dpms_fgr.dpmscond==1) {
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 75 if(++tdpms100ms>30) // 3sec dpms_fgr.dpmsstart=1; } else if(time_fgr.chksvtime==1 && !(--tsave100ms)) { time_fgr.chksvtime=0; // 2sec eeprom_fgr.datasave=1; } if(time_fgr.keyactive==1 && !(--tkeyact100ms)) time_fgr.keyactive=0; // 7sec } } // multi-master iic.bus interrupt (ddc & fa) // interrupt [ddcnfa_int] void multiiic_interrupt(void) { usch pp_copy, *pt; int edid_addtemp, ddc_addtemp; static usch *rxbuf_addr; static usch rxcntr; static struct reg { usin reva0address : 1; } iic_fgr; _sb1(); pp_copy=pp; pp=0; edid_addtemp=(int)edidaddr; ddc_addtemp=(int)ddc_page1; // start address of ram buffer with edid if(bitfals(dcon,ddc1en)) { // ddc2 mode if(bittru(dcsr0,mst)) { // master mode _nop(); } else if(bittru(dcsr0,txd)) { // slave tx mode iic_fgr.reva0address=0; if(bitfals(dcon,ddc1mat)) // ddc1 match m ode ? ddc2bi(); else if(bittru(dcsr0,nack)) { // nack ? // ddc communication error tbdr=0; edidaddr=ddc_page1; // edid <- start address bitclr(dcsr0,txd); // return slave rx mode } else {
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 76 // transmit edid data if(edid_addtemp > (ddc_addtemp+end_ddc)) edidaddr=ddc_page1; tbdr=*edidaddr; edidaddr++; } } // slave receive mode else if(bittru(dcon,ddc1mat) || iic_fgr.reva0address==1) { // slave address = a0h if(bittru(dcsr0,datafld)) { if(rbdr==0x00) { // sub-address=00h ? tbdr=0; edidaddr=ddc_page1; } else { pt=(usch*)rbdr; // ramdom addressing case tbdr=*pt; edidaddr=ddc_page1+rbdr; } } else // address field iic_fgr.reva0address=1; } else { // slave address = 6eh ddc_fgr.ddccmd=1; if(rxcntr++ < 32) // check buffer overflow rxbuf_addr=ddc_rxtxbuf+rxcntr; *rxbuf_addr=rbdr; // receive ddc command/data } vclkcntr=0; // ddc1 recover timer ddc_fgr.ddc2b=1; // change ddc1 to ddc2 mode } // not yet changed to ddc2b (still ddc1 mode) else if(bitfals(dcon,sclf)) { // edid tx mode if(edid_addtemp > (ddc_addtemp+end_ddc)) edidaddr=ddc_page1; tbdr=*edidaddr; edidaddr++; } else { tbdr=0; edidaddr=ddc_page1; bitclr(dcon,ddc1en); / / ddc -> normal iic } bitclr(dccr,ddcpnd); // clear pending bit pp=pp_copy; _sb0(); } // ddc2bi protocol service
s3c8639/c863a/p863a/c8647/f8647 sync pr ocessor 16- 77 // void ddc2bi(void) { if (bytecnt -- > 1) { tbdr = *txdata; tx buffer pointer txdata++; } else bitclr(dcsr0,txd); // return slave rx mode }
sync processor s3c8 639/c863a/p863a/c8647/f8647 16- 78 notes
s3c8639/c863a/p863a/c8647/f8647 ddc module 17- 1 1 7 ddc module overview the s3c8639/c863a/c8647 microcontroller support s the ddc (display data channel) interface. a pair of serial data (sda 0 ) and serial clock (scl 0 ) line (except ddc1 mode) is provided to carry information between the master and peripheral that are connected to the bus. the sda0 and scl0 lines are bi-directional. the ddc1 mode uses vertical sync input at the vsync-i or vclk (vclk is input-only). ddc1 is implemented physically using vclk input and sda0 output. protocols for the ddc2b, ddc2bi, and ddc2b+ are supported in hardware by multi-master iic-bus logic and in software by the edid (extended display identification) and vdif (video display interface) formats. to control ddc interface, you write values to the following registers: ? ddc control register, dcon ? ddc clock control register, dccr ? ddc control/status registers 0,1, dcsr0,1 ? ddc data shift register, ddsr ? ddc address registers 0,1, dar0,1 ? transmit pre-buffer data register, tbdr ? receive pre-buffer data register, rbdr
ddc module s3c8639/c863a/p863a /c8647/f8647 17- 2 dd c control register (dcon) the programmable dcon register to control the ddc is located at e9h in set 1, bank 1. it is read/write addressable. only four bits are mapped in this register. the dcon.0 setting lets you detect falling edges at the serial clock, scl0. if the dcon.0 is set to "0", the scl0 (serial clock) is still high after reset (when read), or the bit can be cleared by s/w written "0" (when write). if the dcon.1 is set to "1", falling edge is detected at scl0 pin after reset or after this bit is cleared by s/w. note when the ddc interrupt is occurred, scl0 line is not pull-down at the following cases: ? ddc1 mode ? tx/rx pre-buffer data registers ?enable? bit, dcon.3 i s "1" (only slave mode). the dcon.1 setting lets you select normal iic-bus interface mode or ddc1 transmit mode. if you select normal iic-bus interface mode (dcon.1 = "0"), scl0 pin is selected for clock line and the scl0 falling edge (sclf) interrupt is disabled. or if you select ddc1 transmit mode (dcon.1 = "1"), vclk pin is selected for clock line and the sclf interrupt is enable. the dcon.2 is a ddc address match bit and read-only. when the received ddc address matches to dar0 register, dcon.2 is "1". and when it is start, stop or reset condition, dcon.2 is "0". to enable transmit or receive pre-buffer data register, dcon.3 is used. when the transmit or receive pre-buffer data register is not used, dcon.3 is "0" (normal iic-bus mode). dcon.3 is set by writing one to it or by reset. if dcon.3 is "1", the transmit or receive pre-buffer data register is enable. ddc control register (dcon) e9h, set 1, bank 1, r/w (bit 2 is read-only) - - - - .3 .2 .1 .0 msb lsb scl0 (serial clock) falling edge detection bit (sclf): 0 = scl0 is high after reset (when read) 0 = cleared by s/w written "0" (when write) 1 = falling edge is detected (when read) 1 = no effect (when write) not used for the s3c8639/c863a/c8647 ddc1 transmit mode enable bit: 0 = iic-bus interface mode (scl0 pins is also selected) 1 = ddc1 transmit mode (vclk pin is also selected) transmit or receive pre-buffer data register enable bit: 0 = normal iic-bus mode (pre-buffer data registers are not used) 1 = pre-buffer data registers enable mode (this bit is set by writing one to it or by reset) ddc address match bit (read-only): 0 = when start or stop or reset 1 = when the received ddc address matches to dar0 register figure 1 7- 1. ddc control register ( d con)
s3c8639/c863a/p863a/c8647/f8647 ddc module 17- 3 ddc clock control register ( dccr ) the ddc clock control register, d cc r , is located at eb h in set 1, bank 1 . it is read/write addressable. dccr settings control the following functions: ? cpu acknowledge signal (ack) enable or suppress ? ddc clock source selection (f osc /10 or f osc /256) ? ddc interrupt enable or disable ? ddc interrupt pending control ? 4-bit prescaler for the serial clock (scl0) when dccr.7 bit is set to " 1 " , it is enable to acknowledgment signal. dccr.6 is bit for transmit clock source selection by f osc /1 0 or f osc /256. dccr.3?dccr.0 bits (ccr3?ccr0) are 4-bit prescaler for the transmit clock (scl0). the scl0 clock may be " stretched " if a slow slave device holds the clock for clock synchronization. in the s3c8639/c863a/c8647 interrupt structure, the ddc interrupt is assigned level irq3, vector eah. to enable this interrupt, you set dccr.5 to " 1 " . program software can then poll the ddc interrupt pending bit(dccr.4) to detect ddc interrupt request. when the cpu acknowledges the interrupt request from the ddc, the interrupt service routine must clear the interrupt pending condition by writing a " 0 " to dccr.4. ddc clock control register (dccr) ebh, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb transmit clock 4-bit prescaler bits: the transmit clock (scl0) frequency is determined by the clock source selection (dccr.6) and this 4-bit prescaler value, according to the following formula: scl0 clock = iicclk/(dccr.3-dccr.0) + 1 where, iicclk is f osc /10 (dccr.6 = "0") or iicclk is f osc /256 (dccr.6 = "1") transmit acknowledge (ack) enable bit: 0 = disable ack generation 1 = enable ack generation transmit clock source selection bit: 0 = f osc /10 1 = f osc /256 ddc module interrupt enable bit: 0 = d isable ddc interrupt 1 = enable ddc interrupt ddc module interrupt pending flag: 0 = when write "0" to this bit (write "1" has no effect) 0 = when dcsr0.4 is "0" 1 = when slave address match occurred 1 = when arbitration lost (master mode) 1 = when a 1-byte transmit or receive operation is terminated 1 = as soon as the ddc1 mode is enable after the prebuffer is used figure 1 7-2 . ddc clock control register ( d cc r )
ddc module s3c8639/c863a/p863a /c8647/f8647 17- 4 table 1 7-1 . sample timing calculations for the ddc transmit clock ( scl0 ) dccr.3?dccr.0 value (iiclk = 4 mhz) iiclk (dccr.3?dccr.0 settings + 1) (f osc = 8 mhz) dccr.6 = 0 (f osc /10) iiclk = 400 khz (f osc = 8 mhz) dccr.6 = 1 (f osc /256) iiclk = 15.625 khz 0000 iiclk/1 400 khz 15.625 khz 0001 iiclk/2 200 khz 7.1825 khz 0010 iiclk/3 133.3 khz 5.2038 khz 0011 iiclk/4 100 khz 3.9063 khz 0100 iiclk/5 80.0 khz 3.1250 khz 0101 iiclk/6 66.7 khz 2.6042 khz 0110 iiclk/7 57.1 khz 2.2321 khz 0111 iiclk/8 50.0 khz 1.9531 khz 1000 iiclk/9 44.4 khz 1.7361 khz 1001 iiclk/10 40.0 khz 1.5625 khz 1010 iiclk/11 36.4 khz 1.4205 khz 1011 iiclk/12 33.3 khz 1.3021 khz 1100 iiclk/13 30.8 khz 1.2019 khz 1101 iiclk/14 28.7 khz 1.1160 khz 1110 iiclk/15 26.7 khz 1.0417 khz 1111 iiclk/16 25.0 khz 0.9766 khz
s3c8639/c863a/p863a/c8647/f8647 ddc module 17- 5 ddc control/status r egister 0 ( d c sr0 ) the ddc control/status register 0 , d c sr0 , is located at ec h in set 1, bank 1 . it is read/write addressable. although the dcsr0 register is read/write addressable, four bits are read only: dcsr0.3?dcsr0.0. dcsr0 register settings are used to control or monitor the following functions: ? master/sla ve transmit or receive mode selection ? bus busy status flag ? ddc module enable or disable ? failed bus arbitration procedure status flag ? received address register match status flag ? last received bit status flag (no ack = " 1 " , ack = " 0 " ) dcsr0.3 is automatically set to "1" when a bus arbitration procedure fails over serial i/o interface, while the iic- bus is set to master mode. if slave mode is selected, dcsr0.3 is automatically set to "1" if the value of dcsr0.7?.4 are changed by program when the busy signal bit, dcsr0.5 is "1", and the ddc address/data field classification bit, dcsr0.2 is "0". when the ddc module is transmitting a one to sda0 line but detected a zero from sda0 line in master mode at the slave mode, dcsr0.3 is set. ddc control/status register 0 (dcsr0) ech, set 1, bank 1, r/w (bit 3-0 is read-only) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb ddc module enable bit: 0 = disable ddc module 1 = enable ddc module master/slave tx/rx mode selection bits: 00 = slave receive mode (default mode) 01 = slave transmit mode 10 = master receive mode 11 = master transmit mode bus busy signal bit: 0 = bus is not busy (when read) 0 = stop condition generation (when write) 1 = bus is busy (when read) 1 = start condition generation (when write) arbitration lost bit: 0 = bus arbitration status okay 1 = bus arbitration failed during serial i/o received acknowledgement (ack) bit: 0 = ack is received 1 = ack is not received not used for the s3c8639/c863a ddc address/data field classification bit: 0 = when reset or start/stop, or when the received data is in the data field. 1 = when received slave address matches to dar0, dar1 register or general call figure 1 7-3 . ddc control /status register 0 ( d c sr0 )
ddc module s3c8639/c863a/p863a /c8647/f8647 17- 6 ddc control/status re gister 1 ( dcsr1 ) the ddc control/status register 1, called dcsr1, is located at ed h in set 1, bank 1 . it is read/write addressable. only three bits are mapped in this register. two bits are read-only: dcsr1.1 and dcsr1.0. dcsr1 register settings are used to control or monitor the following functions: ? stop condition detection flag ? data buffer empty status flag ? data buffer full status flag ddc control/status register 1 (dcsr1) edh, set 1, bank 1, r/w (bits 1 and 0 are read-only) - - - - - .2 .1 .0 msb lsb data buffer full status bit: 0 = when the cpu reads the received data from the rbdr register or stop condition 1 = when thd data or matched address is transferred from the ddsr register to the rbdr register not used for the s3c8639/c863a/c8647 data buffer empty status bit: 0 = when the cpu writes the transmitting data into the tbdr register 1 = when the data of the tbdr register loads to the ddsr register or when a stop condition is detected in pcsr0.7-6 (slave transmission mode) = "01" stop condition detection bit: 0 = when it writes "0" to this bit, and reset or master mode 1 = when a stop condition isdetected after start and slave address reception figure 1 7-4 . ddc control/status register 1 ( dcsr1 )
s3c8639/c863a/p863a/c8647/f8647 ddc module 17- 7 ddc data shift register ( ddsr ) the ddc data shift register for ddc interface, called ddsr, is located at f1 h in set 1, bank 1 . it is read/write addressable. the transmitted data output serially from most significant bit (msb) after writing a data to ddsr. in addition, the received data from the iic-bus input to ddsr serially from least significant bit (lsb). ddsr register capable to write while dcsr0.4 is set to " 1 " and dcon.3 is set to " 0 " , and to read anytime regardless of icsr0.4. ddc data shift register (ddsr) f1h, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb 8-bit data shift register for ddc tx/rx operations: write enable when dcsr0.4 is "1" and dcon.3 is "0". read enable anytime. figure 1 7-5 . ddc data shift register ( ddsr )
ddc module s3c8639/c863a/p863a /c8647/f8647 17- 8 ddc address register 0 ( dar0 ) the ddc address register 0 for ddc interface, called dar0, is located at ea h in set 1, bank 1 . it is read/write addressable. this register is consisted of 4-bit slave address latch (dar0.3?dar0.0 is not mapped at the s3c8639/c863a/c8647). dar0 register is capable to write when dcsr0.4 is " 0 " , and to read anytime regardless of dcsr0.4. 4-bits of the dar0 register are operate only when receive the slave address. ddc address register 0 (dar0) eah, set 1, bank 1, r/w .7 .6 .5 .4 - - - - msb lsb 4-slave address bits: these bits are operated only when receive the slave address. write enable when dcsr0.4 is "0". read enable anytime. not used for the s3c8639/c863a/c8647 figure 1 7-6 . ddc address register 0 ( dar0 ) ddc address register 1 ( dar1 ) the ddc address register 1 for ddc interface, called dar1, is located at ee h in set 1, bank 1 . it is read/write addressable. this register is consisted of 7-bit slave address latch (dar1.0 is not mapped at the s3c8639/c863a/c8647). dar1 register is capable to write when dcsr0.4 is " 0 " , and to read anytime regardless of dcsr0.4. 7-bits of the dar1 register are operate only when receive the slave address. ddc address register 1 (dar1) eeh, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 - msb lsb 7-slave address bits: these bits are operated only when receive the slave address. write enable when dcsr0.4 is "0". read enable anytime. not used for the s3c8639/c863a/c8647 figure 1 7-7 . ddc address register 1 ( dar1 )
s3c8639/c863a/p863a/c8647/f8647 ddc module 17- 9 transmit pre-buffer data register ( tbdr ) the transmit pre-buffer data register, called tbdr, is located at efh in set 1, bank 1. it is read/write addressable. tbdr register is capable to write when dcsr0.4 is "1", and to read anytime regardless of dcsr0.4. when dcon.3 (tbdr enable bit) = "1" and dcsr1.1 = "0", the data written into this register will be automatically downloaded to the ddc data shift register (ddsr) and generate the interrupt request when the module detects the calling address is matched and the bit 0 of the received data is "1" (dcsr0.7-6 = "01") and when the data in the ddsr register has been transmitted with received acknowledge bit, dcsr0.0 = "0". at this interrupt service routine, the cpu must write the next data to the tbdr register to clear dcsr1.1 and for the auto downloading of data to the ddsr register after the data in the ddsr register is transmitted over again with dcsr0.0 = "0". when dcon.3 = "1" and dcsr1.1 = "1", the data stored in this register will not be downloaded to the module detects the calling address is matched and the bit 0 of the received data is "1". at this interrupt service routine, the cpu must write the current data and rewrite the next data to the tbdr register to clear dcsr1.1. if the master receiver doesn't acknowledge the transmitted data, dcsr0.0 = "1", the module will release the sda line for master to generate stop or repeated start conditions. if dcon.3 (tbdr enable bit) is "0", the module will pull-down the scl line in the iic-bus interrupt service routine when the dcsr0.2 is "1". and the module will release the scl line if the cpu writes a data to the ddsr registers and the interrupt pending bit is cleared. transmit pre-buffer data register (tbdr) efh, set 1, bank 1, r/w .7 .6 .5 .4 .5 .3 .2 .1 msb lsb 8-bit transmit pre-buffer data register: write enable when dcsr0.4 is "1". read enable anytime. figure 1 7-8 . transmit pre-buffer data register ( tbdr )
ddc module s3c8639/c863a/p863a /c8647/f8647 17- 10 receive pre-buffer data register ( rbdr ) the receive pre-buffer data register, called rbdr, is located at f0 h in set 1, bank 1 . it is read-only addressable. rbdr register is capable to read anytime. rbdr register will be updated after a data byte is received when the dcsr0.2 is "1"and the dcsr1.0 will be "1". the read operation of rbdr register will clear the dcsr1.0. after the dcsr1.0 is cleared, the register can load the received data again and set the dcsr1.0. receive pre-buffer data register (rbdr) f0h, set 1, bank 1, read only .7 .6 .5 .4 .5 .3 .2 .1 msb lsb 8-bit receive pre-buffer data register: it is read only register. read enable anytime. figure 1 7-9 . receive pre-buffer data register ( rbdr ) sda d7 ack d0 d6 d7 1st 2nd 8th 9th 1st t v t l t h max. 25 khz t v t v t v where, t v = data valid time (min. 30 us) t h = vclk high pulse width (min. 20 us) t l = vclk low pulse width (min. 20 us) (max. vclk input frequency = 25 khz) note: msb (most significant bit) first output in each bytes. vclk figure 1 7-10 . ddc1 mode timing diagram ( one-byte transfer )
s3c8639/c863a/p863a/c8647/f8647 ddc module 17- 11 iic-bus control logic (dccr, dcsr0, dcsr1) receive pre-buffer data register (rbdr) 0 1 data bus ddc control logic scl0 "ddc1en" ddc data shifter (ddsr) sda0 comparator address register (dar0) (dar1) irq3 0 1 0 1 transmit pre-buffer data register (tbdr) "bufen" irq3 vsync-i (from sync processor) (vclk = max. 25 khz) figure 1 7-11 . ddc module block diagram
ddc module s3c8639/c863a/p863a /c8647/f8647 17- 12 the ddc interface ddc2bi mode overview ddc2b capable graphic hosts have limited and mono-directional communications with the display devices. at the contrary, ddc2bi mode is an extension of the ddc2b level in order to offer a bi-direction communication between the computer graphic host and the display device. ddc2bi brings ddc2b+ functionality to ddc2b graphic hosts using a simple s/w driver. so ddc2bi display device is made by simple s/w upgrade to ddc2b+ capable displays. ddc2bi protocol relies on the ddc2b h/w definition and the access bus messages protocol. the graphic host behaves as an iic single master host, and the display device behaves as an iic slave device. the ddc2bi is a modification of the access bus multi-master protocol to fit single master communication. ddc2bi host and display device ddc2bi host is considered as an iic single master capable device. the virtual iic slave address of the host is 50/51h. but ddc2bi display device is considered as a fixed address display device (6e/6f), and uses only iic slave mode to communicate with the host. a display dependent devices are geographically located around the display and follow the same ddc2bi data protocol than the display device. and fixed address iic slave devices group all the existing stand-alone and brain-less iic slave device. these devices can coexist and be connected to the ddc/iic-bus. ddc2bi s/w implementation in order to describe the display that the received message is of ddc2bi type, the source address byte bit 0 is set. and when the host expects an answer from the display, the host reads the answer message at the display device slave address 6fh. the checksum is still computed by using the 50h, virtual host address. a null message can be defined as an access bus message without any data byte. the null message is used in the following cases: ? to detect that the display is ddc2bi capable by reading it at 6fh, iic slave address. ? to describe the host that the display does not have any answer to give to the host ? the enable application report has not been sent prior application messages exchange with the host ddc2bi communication in the ddc2bi communication, it is capable to retrials when a communication fails (bus error or bad checksum). so the host is responsible for resending its message and trying to get an answer from the display again. when the communication fail is occurred, the ddc2bi devices must answer by the retry of host. the ddc2bi capable device must properly send and receive all its supported messages. this determines the maximum internal data communication buffer required size for proper display operation. if the device receive a message which size is lager than the maximum supported by the device, the message be accepted entirely by the device, but does not need to be supported internally, and then be discarded. therefore the ddc2bi capable device must acknowledge all received data bytes from the host.
s3c8639/c863a/p863a/c8647/f8647 ddc module 17- 13 the iic-bus interface the s3c8639/c863a/c8647 iic-bus interface has four operating modes: ? master transmitter mode ? master receive mode ? slave transmitter mode ? slave receive mode functional relationships between these operating modes are described below. start and stop conditions when the iic-bus interface is inactive, it is in slave mode. the interface is therefore always in slave mode when a start condition is detected on the sda line. (a start condition is a high-to-low transition of the sda line while the clock signal, scl, is high level.) when the interface enters master mode, it initiates a data transfer and generates the scl signal. a start condition initiates a one-byte serial data transfer over the sda line and a stop condition ends the transfer. (a stop condition is a low-to-high transition of the sda line while scl is high level.) start and stop conditions are always generated by the master. the iic-bus is ?busy? when a start condition is generated. a few clocks after a stop condition is generated, the iic -bus is again ?free?. when a master initiates a start condition, it sends its slave address onto the bus. the address byte consists of a 7-bit address and a 1-bit transfer direction indicator (that is, write or read). if bit 8 is ?0?, a transmit operation (write) is indicated; if bit 8 is ?1?, a request for data (read) is indicated. the master ends the indicated transfer operation by transmitting a stop condition. if the master wants to continue sending data over the bus, it can the generate another start condition and another slave address. in this way, read-write operations can be performed in various formats.
ddc module s3c8639/c863a/p863a /c8647/f8647 17- 14 stop condition start condition sclk sda in figure 17-12 . start and stop conditions start condition hold time data must remain stable while clock is high change of data allowed stop condition setup data must remain stable while clock is high start condition hold time figure 17-13 . input data protocol
s3c8639/c863a/p863a/c8647/f8647 ddc module 17- 15 data transfer formats every byte put on the sda line must be eight bits in length. the number of bytes which can be transmitted per transfer is unlimited. the first byte following a start condition is the address byte. this address byte is transmitted by the master when the iic-bus is operating in master mode. each byte must be followed by an acknowledge (ack) bit. serial data and addresses are always sent msb first. single byte write mode format data transferred (data + acknowledge) a data a p a sub address a data multigle byte write mode format a data a p data transferred (data n + acknowledge) auto increment of sub address single byte read mode format data transferred (data + acknowledge) a data a p a sub address a multigle byte read mode format notes: 1. s: start, a: acknowledge, p: stop 2. the "sub address" indicates the internal address of the slave device. slave address data a p a data a data transferred (data n + acknowledge) r s slave address w "0" (write) s slave address w "0" (write) s slave address r "1" (read) s slave address w "0" (write) s figure 17-14 . iic-bus interface data formats
ddc module s3c8639/c863a/p863a /c8647/f8647 17- 16 ack signal transmission to complete a one-byte transfer operation, the receiver must send an ack bit to the transmitter. the ack pulse occurs at the ninth clock of the scl line (eight clocks are required to complete the one-byte transfer). the clock pulse required for the transmission of the ack bit is always generated by the master. the transmitter releases the sda line (that is, it sends the sda line high) when the ack clock pulse is received. the receiver must drive the sda line low during the ack clock pulse so that sda is low during the high period of the ninth scl pulse. the ack bit transmit function can be enabled and disabled by software ( d ccr.7). however, the ack pulse on the ninth clock of scl is required to complete a one-byte data transfer operation. sclk from master clock to output data output from transmitter data output from receiver clock to output ack 9 8 1 start condition figure 17-15 . acknowledge response from receiver
s3c8639/c863a/p863a/c8647/f8647 ddc module 17- 17 read-write operations when operating in transmitter mode, the iic-bus interface interrupt routine waits for the master (the ks88c6332/c6348 ) to write a data byte into the iic-bus data shift register ( d dsr). to do this, it holds the scl line low prior to transmission. in receive mode, the iic-bus interface waits for the master to read the byte from the iic-bus data shift register ( d dsr). it does this by holding the scl line low following the complete reception of a data byte. bus arbitration procedures arbitration takes place on the sda line to prevent contention on the bus between two masters. if a master with a sda high level detects another master with an sda active low level, it will not initiate a data transfer because the current level on the bus does not correspond to its own. the master which loses the arbitration can generate scl pulses only until the end of the last-transmitted data byte. the arbitration procedure can continue while data continues to be transferred over the bus. the first stage of arbitration is the comparison of address bits. if a master loses the arbitration during the addressing stage of a data transfer, it is possible that the master which won the arbitration is attempting to address the master which lost. in this case, the losing master must immediately switch to slave receiver mode. abort conditions if a slave receiver does not acknowledge the slave address, it must hold the level of the sda line high. this signals the master to generate a stop condition and to abort the transfer. if a master receiver is involved in the aborted transfer, it must also signal the end of the slave transmit operation. it does this by not generating an ack after the last data byte received from the slave. the slave transmitter must then release the sda to allow a master to generate a stop condition. configuring the iic-bus to control the frequency of the serial clock (scl), you program the 4-bit prescaler value in the dc cr register. the iic-bus interface address is stored in iic-bus address register, d iar 0/dar1 . (by default, the iic-bus interface address is an unknown value.)
ddc module s3c8639/c863a/p863a /c8647/f8647 17- 18 notes
s3c8639/c863a/p863a/c8647/f8647 slave iic-bus inter face 18-1 18 slave iic-bus interface ( only s3c863x) overview the s3c8639/c863a microcontroller supports a slave only iic-bus serial interface. a dedicated serial data line (sda) and a serial clock line (scl) carry information between bus master and slave devices which are connected to the iic-bus. the sda is bi-directional. but in the s3c8639/c863a/c8647, the scl line is uni-directional (input only). s3c8639/c863a microcontroller can receive and transmit serial data to and from master. when the iic-bus is free, the sda and scl lines are both at high level. to control slave-only iic-bus operations, you write values to the following registers: ? slave only iic-bus control/status register, sicsr ? slave only iic-bus tx/rx data shift register, sidsr ? slave only iic-bus address register, s iar start and stop conditions are always generated by the master. a 7-bit address value in the first data byte that is put onto the bus after the start condition is initiated determines which slave device the bus master selects. the 8th bit determines the direction of the transfer (read or write). every data byte that is put onto the sda line must total eight bits. the number of bytes which can be sent or received per bus transfer operation is unlimited. refer to the iic-bus interface (slave tx/rx) of chapter 17 for the protocol of the slave iic-bus at the s3c8639/c863a.
slave iic-bus interface s3c8639/c863a/p863a /c8647/f8647 18- 2 slave only iic-bus control/status register ( sicsr) the slave only iic-bus control/status register, sicsr , is located in set 1 , bank 1, at address f2 h. sicsr register settings are used to control or monitor the following slave iic-bus functions (see f igure 18- 4): ? s lave iic-bus acknowledge ment (ack) signal generation enable or suppress ? s lave iic-bus module enable ? s lave iic-bus tx/rx interrupt enable ? s lave iic-bus tx/rx interrupt pending condition control ? slave iic-bus tx/rx mode status detect/control ? slave iic-bus busy status detect ? slave iic-bus address match status detect ? received acknowledge signal detect (no ack = ?1?, ack = ?0?) lsb msb slave only iic-bus control/status register (sicsr) f2h, set 1, bank 0, r/w slave iic-bus tx/rx interrupt pending bit: 0 = no interrupt pending (when read), clear pending condition (when write) 0 = when sicsr.6 is "0" 1 = when 1-byte tx/rx is terminated 1 = when slave address match occurred slave iic-bus acknowledgement (ack) enable bit: 0 = disable ack generation 1 = enabel ack generation slave iic-bus tx/rx interrupt enable bit: 0 = disable interrupt 1 = enable interrupt iic-bus busy status bit: 0 = iic-bus is not busy 1 = iic-bus is busy slave address match bit : 0 = when start or stop or reset condition is generated 1 = when received slave address value matches to siar register slave iic-bus last received bit status flag: 0 = last-received bit is "0" (ack was received) 1 = last-received bit is "1" (ack was not received) .7 .6 .5 .4 .3 .2 .1 .0 slave iic-bus module enable bit: 0 = disable iic-bus module 1 = enabel iic-bus module (enable serial data tx/rx) slave iic-bus tx/rx mode status bit: 0 = slave receiver mode (default mode) 1 = slave transmitter mode figure 18 -1. slave only iic-bus control/status register ( sicsr )
s3c8639/c863a/p863a/c8647/f8647 slave iic-bus inter face 18- 3 slave only iic-bus transmit/receive data shift register ( sidsr ) the slave iic-bus data shift register, sidsr , is located in set 1, bank 1, at address f4h . in a transmit operation, data that is written to the iic is transmitted serially . the sicsr.6 setting enables or disables serial transmit/receive operations. when sicsr.6 = ?1?, data can be written to the shift register. the slave iic-bus shift register can, however, be read at any time, regardless of the current sicsr.6 setting. lsb msb slve only iic-bus transmit/receive data shift register (sidsr) f4h, set 1, bank 1, r/w when sicsr, 6 = "0", write operation is enabled. you can read the sidsr data value at anytime, regardless of the current sicsr.6 setting. .7 .6 .5 .4 .3 .2 .1 .0 8-bit data shift register for slave iic-bus tx/rx operations: figure 18 - 2 . slave only iic-bus tx/rx data shift register ( sidsr ) slave only iic-bus address register ( s iar) the address register for the iic-bus interface, s iar, is located, in set 1, bank 1, at address f3 h. it is used to store a latched 7 -bit slave address. this address is mapped to iar.7 ?iar.1; bit 0 is not used (see f igure 18-3 ). the latched slave address is compared to the next received slave address . lsb msb slave only iic-bus address register (siar) f3h, set 1, bank 1, r/w these bits are operate only when receive the slave address. when sicsr.6 = "0", read operation is enabled. you can read the sidsr data value at any time, regardless of the current sicsr.6 setting. .7 .6 .5 .4 .3 .2 .1 - 7-bit slave address, latched from the iic-bus not used for the s3c8639/c863a figure 18 - 3 . slave only iic-bus address register ( s iar)
slave iic-bus interface s3c8639/c863a/p863a /c8647/f8647 18- 4 data shifter (sidsr) iic-bus control logic (sicsr) scl1 sda1 comparator address register (siar) irq7 data bus note: the iic-bus interrupt (irq7) is generated when a 1-byte receive or transmit operation is terminated before the shift operation has been completed. figure 18 -4. iic-bus block diagram
s3c8639/c863a/p863a/c8647/f8647 electri cal data 19- 1 19 electrical data overview in this section, s3c8639/c863a/c8647 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? d.c. electrical characteristics ? data retention supply voltage in stop mode ? stop mode release timing when initiated by a reset ? i/o capacitance ? a/d converter electrical characteristics ? a.c. electrical characteristics ? input timing measurement points for p0.0?p0.2 and tm0cap ? oscillation characteristics ? oscillation stabilization time ? clock timing measurement points for x in ? schmitt trigger characteristics ? power-on reset circuit characteristics
electrical data s3c 8639/c863a/p863a/c8647/f8647 19- 2 table 19-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i1 type g-3 (n-channel open drain) ? 0.3 to + 7.0 v i2 all port pins except v i1 ? 0.3 to v dd + 0.3 output voltage v o all output pins ? 0.3 to v dd + 0.3 output current high i oh one i/o pin active ? 10 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 total pin current except port 3 + 100 sync-processor i/o pins and iic-bus clock and data pins + 150 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 table 19-2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v (s3c863x), v dd = 4.0 v to 5.5 v (s3c8647)) parameter symbo l conditions min typ max unit input high v ih1 all input pins except v ih2 , v ih3 and v ih4 0.8 v dd ? v dd v voltage v ih2 x in v dd ?0.5 v dd v ih3 ttl input (hsync-i, vsync-i, and csync-i) 2.0 v dd v ih4 scl0/sda0, scl1/sda1 0.7v dd v dd input low v il1 all input pins except v il2 and v il3 ? 0.2 v dd voltage v il2 x in 0.4 v il3 ttl input (hsync-i, vsync-i, and csync-i) 0.8 v il4 scl0/sda0, scl1/sda1 0.3v dd output high voltage v oh1 v dd = 5 v 10%; i oh = ? 15 ma (s3c863x), i oh = ? 14 ma (s3c8647); port 3.6?3.7 v dd ? 1.2 ? v oh2 v dd = 5 v 10%; i oh = ? 4 ma (s3c863x), i oh = ?3.6 ma (s3c8647); port 1.2, port 3.0?3.5 v oh3 v dd = 5 v 10%; i oh = ? 2 ma; port 0, 2, clamp-o, h, and vsync-o v dd ? 1.0 v oh4 v dd = 5 v 10%; i oh = ? 6 ma; port 1.0?p1.1, scl0 and sda0
s3c8639/c863a/p863a/c8647/f8647 electri cal data 19- 3 table 19-2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v (s3c863x), v dd = 4.0 v to 5.5 v (s3c8647)) parameter symbol conditions min typ max unit output low voltage v ol1 v dd = 5 v 10%; i ol = 15 ma port 3.6 ?3.7 ? ? 0.4 v v ol2 v dd = 5 v 10%; i ol = 4 ma port 3.0?3.5 and port 1.2 0.4 v ol3 v dd = 5 v 10%; i ol = 2 ma port 0, 2, clamp-o, h, and vsync-o 0.4 v ol4 v dd = 5 v 10%; i ol = 6 ma port 1.0?1.1; scl0 and sda0 0.6 input high leakage current i lih1 v in = v dd all input pins except x in , x out ? ? 3 a i lih2 v in = v dd ; x out only ? ? 20 i lih3 v in = v dd ; x in only 2.5 6 20 input low leakage current i lil1 v in = 0 v; all input pins except x in , x out , reset , hsynci & vsynci ? ? ? 3 i lil2 v in = 0 v; x out only ? ? ? 20 i lil3 v in = 0 v; x in only ? 2.5 ? 6 ? 20 output high leakage current i loh1 v out = v dd ? ? 3 output low leakage current i lol1 v out = 0 v ? ? ? 3 pull-up resistor r u1 v in = 0 v; v dd = 5 v 10% ports 3.7?3.4 20 47 80 k w r u2 v in = 0 v; v dd = 5 v 10% reset only 150 280 480 pull-down resistor r d v in = 0 v; v dd = 5 v 10% hsynci & vsynci 150 300 500 supply current (note) i dd1 v dd = 5 v 10% operation mode; 12 mhz crystal c1 = c2 = 22pf ? 10 20 ma i dd2 v dd = 5 v 10% idle mode; 12 mhz crystal c1 = c2 = 22pf 4 8 i dd3 v dd = 5 v 10% stop mode 100 150 a note: supply current does not include drawn internal pull-up/pull-do wn resistors and external loads of output.
electrical data s3c 8639/c863a/p863a/c8647/f8647 19- 4 table 19-3. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2 ? 5.5 v data retention supply current i dddr stop mode, v dddr = 2.0 v ? ? 5 a notes : 1. during the oscillator stabilization wait time (t wait ), all cpu operations must be stopped. 2. supply current does not include drawn through internal pull?up resistors and external output current loads. note: t wait is the same as 4096 x 16 x 1/f osc . execution of stop instrction reset occurs ~ ~ v dddr ~ ~ stop mode oscillation stabilzation time data retention mode t wait reset v dd normal operating mode figure 19-1. stop mode release timing when initiated by a reset table 19-4. input/output capacitance (t a = ?40 c to + 85 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io
s3c8639/c863a/p863a/c8647/f8647 electri cal data 19- 5 table 19-5. a/d converter electrical characteristics (s3c863x) (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? 8 ? bit total accuracy v dd = 5 v conversion time = 5 m s ? ? 2 lsb integral linearity error ile av ref = 5 v ? 1 differential linearity error dle av ss = 0 v ? 1 offset error of top eot 1 2 offset error of bottom eob 0.5 2 conversion time (1) t con 8-bit conversion 48 x n/f osc (3) , n = 1, 4, 8, 16 20 ? 170 m s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 1000 ? m w analog reference voltage av ref ? 2.5 ? v dd v analog ground av ss ? v ss ? v ss + 0.3 v analog input current i adin av ref = v dd = 5v ? ? 10 m a analog block current (2) i adc av ref = v dd = 5v ? 1 3 ma av ref = v dd = 3v 0.5 1.5 ma av ref = v dd = 5v when power down mode 100 500 na notes: 1. "conversion time" is the time required from the moment a conversion operation starts until it ends. 2. i adc is an operating current during the a/d conversion. 3. f osc is the main oscillator clock.
electrical data s3c 8639/c863a/p863a/c8647/f8647 19- 6 table 19-6 . a/d converter electrical characteristics (s3c8647) (t a = ? 4 0 c to + 85 c, v dd = 4.0 v to 5 . 5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? ? 4 ? bit absolute accuracy (1) ? 4 bit conversion 24 x n/f osc (3) , n = 1, 4, 8, 16 ? ? 0.5 lsb conversion time (2) t con 3 ? ? us analog input voltage v ian ? v ss ? v dd v analog input impedance r an ? 2 ? ? m w notes: 1. excluding quantization error, absolute accuracy values are within 0.5 lsb. 2 . " conversion time " is the time required from the moment a conversion operation starts until it ends . 3 . f osc is the mean oscillator clock.
s3c8639/c863a/p863a/c8647/f8647 electri cal data 19- 7 table 19-7. a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v (s3c863x), v dd = 4.0 v to 5.5 v (s3c8647)) parameter symbol conditions min typ max unit noise filter t nf1h t nf1l int0?2 and tm0cap (rc delay) 300 ? ? ns t nf2 reset only (rc delay) 1000 ? ? t nf1h t nf1l 0.8 v dd 0.2 v dd t nf2 figure 19-2. input timing measurement points for p0.0?p0.2 and tm0cap
electrical data s3c 8639/c863a/p863a/c8647/f8647 19- 8 table 19-8. oscillation characteristics (t a = ? 40 c + 85 c) oscillator clock circuit conditions min typ max unit main crystal or ceramic c2 c1 x in x out v dd = 3.0 v to 5.5 v (s3c863x) v dd = 4.0 v to 5.5 v (s3c8647) 8 ? 12 mhz external clock (main) x in x out v dd = 3.0 v to 5.5 v (s3c863x) v dd = 4.0 v to 5.5 v (s3c8647) 8 ? 12 mhz note : the maximum oscillator frequency is 12 mhz. if you use an oscillator frequency higher than 12 mhz, you cannot select a non-divided cpu clock using clkcon settings. that is, you must select one of the divide-by values. table 19-9. oscillation stabilization time (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v (s3c863x), v dd = 4.0 v to 5.5 v (s3c8647)) oscillator test condition min typ max unit crystal v dd = 3.0 v (or 4.0 v) to 5.5 v ? ? 20 ms ceramic v dd = 3.0 v (or 4.0 v) to 5.5v ? ? 10 external clock x in input high and low level width (t xh , t xl ) 25 ? 500 ns note : oscillation stabilization time is the time required for the cpu clock to return to its normal oscillation frequency after a power-on occurs, or when stop mode is released. x in t xh t xl 1/fx v dd - 0.5 v 0.4 v figure 19-3. clock timing measurement points for x in
s3c8639/c863a/p863a/c8647/f8647 electri cal data 19- 9 a = 0.2 v dd b = 0.4 v dd c = 0.6 v dd d = 0.8 v dd v dd v out v ss v in a b c d figure 19-4. schmitt trigger characteristics (normal port; except ttl input) table 19-10. power-on reset circuit characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v (s3c863x), v dd = 4.0 v to 5.5 v (s3c8647)) parameter symbol conditions min typ max unit power-on reset release voltage v ddlvd 2.3 3.1 (2) 2.65 3.4 (2) 3.0 3.7 (2) v power-on reset detection voltage v lvd 2.3 3.1 (2) 2.65 3.4 (2) 3.0 3.7 (2) v power supply voltage off time t off 10 ? ? ms power-on reset circuit consumption current (2) i ddpr v dd = 5 v 10% 100 150 m a v dd = 3.3 v 60 100 m a notes: 1. current contained when power-on reset circuit is provided internally. 2. only s3c8647.
electrical data s3c 8639/c863a/p863a/c8647/f8647 19- 10 t off v ddlvd v lvd v dd figure 19-5. power-on reset timing
s3c8639/c863a/p863a/c8647/f8647 mechanical data 20- 1 20 mechanical data overview the s3c8639/c863a/c8647 microcontroller is available in a 42-pin sdip package (samsung part number 42- sdip-600) and a 44 -qfp package (samsung part number 44-qfp-1010b). note : dimensions are in millimeters. 39.50 max 39.10 0 .2 0.50 0.1 1.778 (1.77) 0.51 min 3.30 0.3 3.50 0.2 5.08 max 42-sdip-600 0-15 1.00 0.1 0.25 + 0.1 - 0.05 15.24 14.00 0 .2 #42 #22 #21 #1 figure 20- 1. 42-pin sdip package dimensions (42-sdip-600)
mechanical data s3c8639/c863a/p863a /c8647/f8647 20- 2 44-qfp-1010b #44 note : dimensions are in millimeters. 10.00 0.2 13.20 0.3 10.00 0.2 13.20 0.3 #1 0.35 + 0.10 - 0.05 0.80 (1.00) 0.10 max 0.80 0.20 0.05 min 2.05 0.10 2.30 max 0.15 + 0.10 - 0.05 0-8 figure 20- 2. 44-pin qfp package dimensions (44-qfp-1010b)
s3c8639/c863a/p863a/c8647/f8647 mechanical data 20- 3 note : dimensions are in millimeters. 27.88 max 27.48 0 .20 (1.37) 32-sdip-400 9.10 0 .20 #32 #1 0.45 0.10 1.00 0.10 3.80 0.20 5.08 max 1.778 0.51 min 3.30 0.30 #17 #16 0-15 0.25 + 0.10 - 0.05 10.16 figure 20-3 . 3 2-pin sdip package dimensions ( 3 2-sdip- 4 00)
mechanical data s3c8639/c863a/p863a /c8647/f8647 20- 4 32-sop-450a 20.30 max 19.90 0 .20 #17 #16 0-8 0.25 + 0.10 - 0.05 11.43 8.34 0.20 0.90 0.20 0.05 min 2.00 0.10 2.20 max 0.10 max 1.27 note : dimensions are in millimeters. 12.00 0 .30 #32 #1 (0.43) 0.40 0.10 figure 20-4 . 3 2-pin sop package dimensions ( 3 2-s o p- 450a )
s3c8639/c863a/p863a/c8647/f8647 s3p863a otp 21- 1 21 s3p863a otp overview the s3p863a single-chip cmos microcontroller is the otp (one time programmable) version of the s3c8639/c863a microcontrollers. it has an on-chip eprom instead of masked rom. the eprom is accessed by serial data format. the s3p863a is fully compatible with the s3c8639/c863a, both in function and in pin configuration. because of its simple programming requirements, the s3p863a is ideal for use as an evaluation chip for the s3c8639/c863a. p0.0/int0 p0.1/int1 p0.2/int2 p0.3 p0.4/tm0cap p0.5 p0.6 p0.7 sdat /p1.0/sda1 sclk /p1.1/scl1 v dd1 v ss1 x out x in v pp /test (gnd) sda0 scl0 reset reset /reset p1.2 p2.0/pwm0 p2.1/pwm1 s3p863a (42-sdip) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p3.7 p3.6 p3.5 p3.4 p3.3/ad3 p3.2/ad2 p3.1/ad1 p3.0/ad0 v dd2 v ss2 p2.7/csync-i (sog) hsync-i vsync-i vsync-o hsync-o clamp-o p2.6/pwm6 p2.5/pwm5 p2.4/pwm4 p2.3/pwm3 p2.2/pwm2 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 note: the bolds indicate an otp pin name. figure 21-1. s3p863a pin assignments (42-sdip package)
s3p863a otp s3c8639/c863a/p863a/c8647/f8647 21- 2 p0.5 p0.6 p0.7 sdat /p1.0/sda1 sclk /p1.1/scl1 v dd1 v ss1 x out x in v pp /test (gnd) sda0 s3p863a (44-qfp) 1 2 3 4 5 6 7 8 9 10 11 p0.4/tm0cap p0.3 p0.2/int2 p0.1/int1 n.c. p0.0/int0 p3.7 p3.6 p3.5 p3.4 p3.3/ad3 44 43 42 41 40 39 38 37 36 35 34 p3.2/ad2 p3.1/ad1 p3.0/ad0 v dd2 v ss2 p2.7/csync-i (sog) hsync-i vsync-i vsync-o hsync-o clamp-o 33 32 31 30 29 28 27 26 25 24 23 scl0 reset reset / reset p1.2 p2.0/pwm0 p2.1/pwm1 p2.2/pwm2 n.c. p2.3/pwm3 p2.4/pwm4 p2.5/pwm5 p2.6/pwm6 12 13 14 15 16 17 18 19 20 21 22 note: the bolds indicate an otp pin name. figure 21-2. s3p863a pin assignments (44-qfp package)
s3c8639/c863a/p863a/c8647/f8647 s3p863a otp 21- 3 table 21-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin number i/o function p1.0 sdat 9 (4) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push- pull output port. p1.1 sclk 10 (5) i serial clock pin. input only pin. test v pp (test) 15 (10) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 18 (13) i chip initialization v dd1 /v ss1 v dd1 /v ss1 11/12 (6/7) i logic power supply pin. v dd should be tied to +5 v during programming. note: parentheses indicate 44-qfp otp pin number. table 21-2. comparison of s3p863a and s3c8639/c863a features characteristic s3p863a s3c8639/c863a program memory 48-kbyte eprom 32/48-kbyte mask rom operating voltage (v dd ) 3.0 v to 5.5 v 3.0 v to 5.5v otp programming mode v dd = 5 v, v pp (test) = 12.5v pin configuration 42 sdip, 44 qfp 42 sdip, 44 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p863a, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 21-3 below. table 21-3. operating mode selection criteria v dd v pp (test) reg/mem address (a15?a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
s3p863a otp s3c8639/c863a/p863a/c8647/f8647 21- 4 d.c. electrical characteristics table 21-4. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v) parameter symbol conditions min typ max unit input high leakage current i lih1 v in = v dd all input pins except x in , x out ? ? 3 a i lih2 v in = v dd ; x out only ? ? 20 i lih3 v in = v dd ; x in only 2.5 6 20 input low leakage current i lil1 v in = 0 v; all input pins except x in , x out , reset , hsync-i and vsync-i ? ? ? 3 i lil2 v in = 0 v; x out only ? ? ? 20 i lil3 v in = 0 v; x in only ? 2.5 ? 6 ? 20 output high leakage current i loh1 v out = v dd ? ? 3 output low leakage current i lol1 v out = 0 v ? ? ? 3 pull-up resistor r u1 v in = 0 v; v dd = 5 v 10% port 3.7?3.4 20 47 80 k w r u2 v in = 0 v; v dd = 5 v 10% reset only 150 280 480 pull-down resistor r d v in = 0 v; v dd = 5 v 10% hsync-i and vsync-i 150 300 500 supply current (note) i dd1 v dd = 5 v 10% operation mode; 12 mhz crystal c1 = c2 = 22pf ? 10 20 ma i dd2 v dd = 5 v 10% idle mode; 12 mhz crystal c1 = c2 = 22pf 4 8 i dd3 v dd = 5 v 10% stop mode 100 150 a note: supply current does not include drawn internal pull-up/pull-down resistors and external loads of output.
s3c8639/c863a/p863a/c8647/f8647 S3F8647 flash mcu 22- 1 22 S3F8647 flash mcu overview the S3F8647 single-chip cmos microcontroller is the flash version of the s3c8647 microcontrollers. it has an on-chip flash rom instead of masked rom. the flash rom is accessed in serial data format. the S3F8647 is fully compatible with the s3c8647, both in function and in pin configuration. because of its simple programming requirements, the S3F8647 is ideal for use as an evaluation chip for the s3c8647. v ss /v ss x out x in v pp /test p0.0/int0 p0.1/int1 reset reset /reset p0.2/int2 p0.4/tm0cap sda scl p2.0/pwm0 p2.1/pwm1 p2.2/pwm2 p2.3/pwm3 p2.4/pwm4 S3F8647 (32-sdip) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd/ v dd p3.7/ sclk p3.6/ sdat p3.5 p3.4 p3.3/ad3 p3.2/ad2 p3.1/ad1 p3.0/ad0 p2.7/csync-i(sog) hsync-i vsync-i vsync-o hsync-o clamp-o p2.5/pwm5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 figure 22-1. S3F8647 pin assignments (32-sdip package)
S3F8647 flash mcu s3c8639/c863a/p863a/c8647/f8647 22- 2 s3c8647 (32-sop) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v ss /v ss x out x in v pp /test p0.0/int0 p0.1/int1 reset reset /reset p0.2/int2 p0.4/tm0cap sda scl p2.0/pwm0 p2.1/pwm1 p2.2/pwm2 p2.3/pwm3 p2.4/pwm4 v dd/ v dd p3.7/ sclk p3.6/ sdat p3.5 p3.4 p3.3/ad3 p3.2/ad2 p3.1/ad1 p3.0/ad0 p2.7/csync-i(sog) hsync-i vsync-i vsync-o hsync-o clamp-o p2.5/pwm5 figure 22-2. S3F8647 pin assignments (32-sop package)
s3c8639/c863a/p863a/c8647/f8647 S3F8647 flash mcu 22- 3 table 22-1. descriptions of pins used to read/write the flash rom main chip during programming pin name pin name pin number i/o function p3.6 sdat 30 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push- pull output port. p3.7 sclk 31 i serial clock pin. input only pin. test v pp (test) 4 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 7 i chip initialization v dd /v ss v dd /v ss 32/1 i logic power supply pin. v dd should be tied to +5 v during programming. table 22-2. comparison of S3F8647 and s3c8647 features characteristic S3F8647 s3c8647 program memory 24-kbyte flash rom 24-kbyte mask rom operating voltage (v dd ) 4.0 v to 5.5 v 4.0 v to 5.5v otp programming mode v dd = 5 v, v pp (test) = 12.5v pin configuration 32 sdip 32 sdip eprom programmability user program 1 time programmed at the factory
S3F8647 flash mcu s3c8639/c863a/p863a/c8647/f8647 22- 4 d.c. electrical characteristics table 22-3. d.c. electrical characteristics (v dd = 4.0 v to 5.5 v) parameter symbol conditions min typ max unit input high leakage current i lih1 v in = v dd all input pins except x in , x out ? ? 3 a i lih2 v in = v dd ; x out only ? ? 20 i lih3 v in = v dd ; x in only 2.5 6 20 input low leakage current i lil1 v in = 0 v; all input pins except x in , x out , reset , hsync-i and vsync-i ? ? ? 3 i lil2 v in = 0 v; x out only ? ? ? 20 i lil3 v in = 0 v; x in only ? 2.5 ? 6 ? 20 output high leakage current i loh1 v out = v dd ? ? 3 output low leakage current i lol1 v out = 0 v ? ? ? 3 pull-up resistor r u1 v in = 0 v; v dd = 5 v 10% port 3.7?3.4 20 47 80 k w r u2 v in = 0 v; v dd = 5 v 10% reset only 150 280 480 pull-down resistor r d v in = 0 v; v dd = 5 v 10% hsync-i and vsync-i 150 300 500 supply current (note) i dd1 v dd = 5 v 10% operation mode; 12 mhz crystal c1 = c2 = 22pf ? 10 20 ma i dd2 v dd = 5 v 10% idle mode; 12 mhz crystal c1 = c2 = 22pf 4 8 i dd3 v dd = 5 v 10% stop mode 100 150 a note: supply current does not include drawn internal pull-up/pull-down resistors and external loads of output.
s3c8639/c863a/p863a/c8647/f8647 S3F8647 flash mcu 22- 5 notes
s3c8639/c863a/p863a/c8647/f8647 development tools 23- 1 23 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7, s 3c9 , s3c8 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, as s embler, and a program for setting options. shine samsung host interface for in - c ircuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm88 the sasm88 is an reloc atable assembler for samsung's s 3c 8-series microcontrollers. the sasm88 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm88 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value " ff " is filled into the unused rom area upto the maximum rom size of the target device automatically. target boards targe t boards are available for all s 3c 8-series microcontrollers. all required target system cables and adapters are included with the device-specific target board.
development tools s3c8639/c863a/p86 3a/c8647/f8647 23- 2 otp s one time programmable microcontroller ( otp) for the s3c8639/c863a microcontroller and otp programmer (gang) are now available. bus smds2+ rs-232c pod probe adapter prom/otp writer unit ram break/display unit trace/timer unit sam8 base unit power supply unit ibm-pc at or compatible tb886332b/6348b (tb8639/863a) target board eva chip target application system figure 23-1 . smds product configuration (smds2+)
s3c8639/c863a/p863a/c8647/f8647 development tools 23- 3 tb88 6332b/6348b (tb8639/863a) target board the tb886332b/6348b (tb8639/863a) target board is used for the s3c8639/c863a microcontroller. it is supported by the smds2+ development system. tb886332b/6348b (tb8639/863a) sm1335b gnd v cc + idle + stop 100-pin connector 25 1 reset to user_v cc off on 74hc11 u1 external triggers ch1 ch2 sw1 smds2+ smds2 144 qfp s3e8630 eva chip j101 50-pin connector 42 1 21 22 j101 50-pin connector 44 1 22 23 figure 23-2 . tb886332b/6348b (tb8639/863a) target board configuration
development tools s3c8639/c863a/p86 3a/c8647/f8647 23- 4 tb88 6424a (tb8647) target board the tb886424a (tb8647) target board is used for the s3c8647 microcontroller. it is supported by the smds2+ development system. tb886424a (tb8647) sm1339a gnd v cc + idle + stop 100-pin connector 25 1 reset to user_v cc off on 74hc11 u1 external triggers ch1 ch2 sw1 smds2+ smds2 144 qfp s3e8630 eva chip j101 50-pin connector 30 1 15 16 figure 23-3 . tb886424a (tb8647) target board configuration
s3c8639/c863a/p863a/c8647/f8647 development tools 23- 5 table 23-1. power selection settings for tb 886332b /tb 886348b (tb8639/863a) " to user_vcc " settings operating mode comments to user_vcc on off target system smds2/smds2+ tb886332b tb886348b (tb8639/863a) v cc v ss v cc the smds2 /smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_vcc on off target system smds2/smds2+ tb886332b tb886348b (tb8639/863a) external v cc v ss v cc the smds2 /smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. table 23-2. power selection settings for tb 886424a (tb8647) " to user_vcc " settings operating mode comments to user_vcc on off target system smds2/smds2+ tb886424a (tb8647) v cc v ss v cc the smds2 /smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_vcc on off target system smds2/smds2+ tb886424a (tb8647) external v cc v ss v cc the smds2 /smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply.
development tools s3c8639/c863a/p86 3a/c8647/f8647 23- 6 smds2+ selection (sam8) in order to write data into program memory that is available in smds2+, the target board should be selected to be for smds2+ through a switch as follows. otherwise, the program memory writing function is not available. table 23-3 . the smds2+ tool selection setting "sw1" setting operating mode smds2 smds2+ smds2+ target board r/w* r/w* table 23-4 . using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the smds2+ breakpoint and trace functions. idle led this led is on when the evaluation chip ( s 3 e 8630 ) is in idle mode. stop led this led is on when the evaluation chip ( s 3 e 8630 ) is in stop mode.
s3c8639/c863a/p863a/c8647/f8647 development tools 23- 7 p0.0/int0 p0.1/int1 p0.2/int2 p0.3 p0.4/tm0cap p0.5 p0.6 p0.7 p1.0/sda1 p1.1/scl1 v dd1 v ss1 test(gnd) sda0 scl0 reset p1.2 p 2.0/pwm0 p2.1/pwm1 p2.2/pwm2 p3.7 p3.6 p3.5 p3.4 p3.3/ad3 p3.2/ad2 p3.1/ad1 p3.0/ad0 v dd2 v ss2 p2.7/csync-i hsync-i vsync-i vsync-o hsync-o clamp-o p2.6/pwm6 p2.5/pwm5 p2.4/pwm4 p2.3/pwm3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40-pin dip connector j101 figure 23-4 . 4 0-pin connector for tb886332b/6348b (tb8639/a) v ss test p0.0/int0 p0.1/int1 reset p0.2/int2 p0.4/tm0cap sda scl p2.0/pwm0 p2.1/pwm1 p2.2/pwm2 p2.3/pwm3 p2.4/pwm4 p2.5/pwm5 v dd p3.7 p3.6 p3.5 p3.4 p3.3/ad3 p3.2/ad2 p3.1/ad1 p3.0/ad0 p2.7/csync-i(sog) hsync-i vsync-i vsync-o hsync-o clamp-o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30-pin dip connector j101 figure 23-5 . 3 0-pin connector for tb886424a (tb8647)
development tools s3c8639/c863a/p86 3a/c8647/f8647 23- 8 target board target system target cable for 42-sdip package part name: ap42sd-g order code: sm6520 40-pin dip connector j101 1 40 20 21 1 40 20 21 1 21 42 22 figure 23-6 . tb886332b/6348b (tb8639/a) adapter cable for 4 2-s di p package target board target system target cable for 30-sdip package part name: ap30sd-g order code: sm6520 30-pin dip connector j101 1 30 15 16 1 30 15 16 1 16 32 17 figure 23-7 . tb886424a (tb8647) adapter cable for 3 2-s di p package

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